Slow, traps studied in Mos dielectrics
11/01/1996
Slow traps studied in MOS dielectrics
Researchers at Griffith University in Australia have developed a new technique for characterizing slow traps in MOS dielectrics. It measures the density and trapping rate of slow traps by stepping the gate voltage of a MOS capacitor in small increments and recording the resulting substrate current transients. Profiles illustrating the trap density as a function of the response time and energy in the silicon bandgap have been successfully obtained to monitor damage caused by electrical stressing and plasma etching.
Slow trapping phenomena in MOS structures have received increasing attention as submicron devices demand thinner oxides and improved quality of the oxide-silicon interface. The slow traps, sometimes called "border traps," exchange charge with the nearby silicon on time scales from milliseconds to hours depending on their energy level and separation from the interface. They are believed to be the main source of surface-induced 1/f noise and random telegraph signals in deep submicron MOSFETs. Under large-signal transient stress conditions in MOS analog devices, threshold voltage shifts are caused by direct tunnel exchange of charge carriers with pre-existing slow traps in the oxide. The increased use of wide bandgap semiconductor materials such as SiC also means that at room temperature, interface traps near the midgap have much longer response times than in silicon and it would be convenient to measure these traps without using higher temperatures.
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Slow trap profile of plasma-etched MOS capacitor shlowing slow traps in the inversion region. The measurement was performed from accumulation to inversion using 50-mV steps.
Slow traps have been studied through hysteresis of high-frequency C-V curves, thermally stimulated currents in MOS capacitors, charge pumping in MOSFETs, and quasi-static C-V measurements. Although quasi-static C-V measurements are commonly used to evaluate the trap density-energy distribution at oxide-silicon interfaces, the presence of slow traps make it difficult to maintain the required equilibrium conditions. Moreover, these current techniques yield either the total trap density or a distribution of trap density in energy but give no information on the response distribution of the traps.
Tanner et. al. have been able to monitor the density, energy location, and response time of slow interface traps at their laboratory in Griffith University, Australia. Their investigations have shown that fresh control samples provide transients lasting no longer than 20 ms at any position in the silicon bandgap, whereas devices that have been subjected to constant current stressing or plasma etching exhibit considerably longer response times at certain energies due to the presence of slow traps. The value of the current at a time >20 ms after a voltage step is a direct measure of the density of slow traps capturing or emitting charge at that instant. The slow trap density can then be easily calculated from the substrate current density, electronic charge, and the voltage step. Alternatively, the voltage can be converted to surface Fermi level to reveal the energy location of the traps and the series of current transients can then provide a direct means of resolving the slow trap density in both energy and response time. The figure shows a typical slow trap profile of a plasma-etched MOS capacitor showing slow traps in the inversion region.
This new technique has been successfully applied to study the defects at different positions at the interface of Si/SiO2 where there is a gradual transition from pure silicon to pure SiO2. The traps due to these defects have response times ranging from nanoseconds close to the silicon conduction or valence bands to milliseconds near the middle of the bandgap. The response time is also affected by the physical separation of the trap from the bulk silicon. The trap density increase in a MOS capacitor due to constant current stressing was measured and the results yield more information on the effects of stressing than could be obtained using the conventional quasi-static C/V technique. Not only were the energies of the traps deduced, their response times and their physical separation from the bulk silicon were readily available.
- M.Y.M.L.