Amkor Electronics enters foundry market
11/01/1997
Amkor Electronics enters foundry market
Amkor/Anam Semiconductor, a division of Amkor Electronics, has begun process qualification at Fab 1 in its new facility in Buchon, South Korea. Fab 1 should reach full capacity in 3Q98. Further expansion is planned as demand warrants, with a Fab 2 schedule to be set in 1998.
The facility, which will ultimately handle more than 25,000, 200-mm wafers/month, replicates a CMOS process from Texas Instruments` DMOS-5 facility in Dallas, TX. TI signed a technology agreement with Amkor in July 1996, and has contracted to purchase a significant portion of the fab`s capacity. Key features of the process include 0.25-?m critical dimensions (0.20-?m gate lengths), shallow trench isolation, five-level interconnect metallization, and CMP planarization.
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Figure 1. The 100 ? 60 m main ballroom at Amkor`s Fab 1. The photo was taken in August, when about half of the planned capacity had been installed.
According to John Weekley, VP of marketing at Amkor Semiconductor, a ballroom layout was chosen for the 6000 m2 cleanroom (Fig. 1) because it provides maximum flexibility. SMIF minienvironments and cassettes, transported on overhead rails (see Fig. 2 on p. S8), provide Class 0.1 cleanliness for the wafers. The cleanroom environment is maintained at Class 10. A separate clean area houses CMP equipment.
Amkor is already a leading supplier of IC packaging, assembly, and test services. The addition of fab capacity makes it one of the first foundries to provide complete turnkey fabrication, from masks (through a joint venture with Photronics) to tested parts.
In the 0.25-?m era, the advent of optical proximity correction and phase shift masks creates complex interactions among the design, mask, and fabrication process. The resulting logistic complexity is daunting, even for captive fabs. While customers will not be limited to Amkor-supplied design libraries, Weekley said the company will assist designers with these integration concerns through its customer support engineering unit in Santa Clara. Customers will have the tools to create their own tooling (e.g. masks, tester source, probe cards) and design (e.g. architecture, cores, compilers) intellectual property.
The 0.25-?m era also brings more challenging packaging requirements (see table). System partitioning among chips, IC architecture and logic design, and manufacturing, assembly, and test are all affected by thermal dissipation, inductance, and other package characteristics. These issues demand a closer relationship between silicon designers and package designers. Amkor, Weekley said, expects to leverage its packaging expertise for foundry customers. Its "Silicon Package Architecture" tools, now under development, will allow customers to incorporate package data in the silicon design flow. The SPA tools also support design for testability and manufacturability.
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Figure 2. Overhead rail for SMIF cassette transport.
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Finally, Weekley said, Amkor expects to partner with its customers, rather than maintaining the traditional arms-length relationship. The Workflow WIP system, for example, provides real time lot tracking. When fully implemented, customers will be able to oversee and control their own production.- K.D.