Japanese research post-DUV lithography
11/01/1997
Japanese research post-DUV lithography
Ed Korczynski, West Coast Editor
With great uncertainty in the direction of post-optical lithography, the worldwide semiconductor industry is evaluating the costs and potential paybacks of investing in fundamentally new technologies. A Japanese government research institute conducted a survey of the Japanese semiconductor industry to quantify the required investment levels, and to suggest specific directions for next-generation lithography infrastructure research.
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Japan`s Kikai Shinko Kyokai (KSK), known in English as the Japan Society for the Promotion of the Machine Industry (JSPMI), is a nonprofit organization under the direction of the Ministry of International Trade and Industry (MITI). The Economic Research Institute of Kikai Shinko Kyokai (ERI-KSK) recently completed a 150-page report that summarizes the prevailing directions of post-optical lithography in Japan. The report`s primary author and editor, Koki Inoue, is acting chief researcher at ERI-KSK.
The report includes an overview of the research activities and perspectives of the main Japanese organizations with influence over semiconductor manufacturing. Top executives at each of the organizations contributed guidance and data (see table).
Both reduction in the size of device structures and increases in silicon wafer sizes have lead to improvements in the cost and performance of ICs. The semiconductor manufacturing industry can take the steps necessary for the migration to larger wafer sizes without additional assistance. However, there are known difficulties in the research and development of core processing technologies for the production of devices with minimum feature sizes below 0.18 ?m. Development of lithography, which is critical for increasing device miniaturization, is particularly problematic.
Cutting-edge R&D (exploratory research or proof-of-concept assessment of different core technologies) for next-generation (0.13-0.10 ?m design rule) lithography consumes more and more resources because traditional optical lithography will soon be unextendible. Since prior lithography minimum linewidth improvements were natural extensions of prior art, significantly less basic research was required. If there was only one obvious post-optical solution, then resource allocation would be relatively simple; unfortunately, there are multiple choices, including x-ray proximity, e-beam (EB) direct write, and EUV.
Currently, all IC manufacturers use the same basic lithographic technology, with the resulting efficiency of pooled resources. In future device generations, it will be impossible for almost all chipmakers to enjoy the same lithography. In the current precompetitive R&D phase, companies tend to wait to commit research resources until other parties` commitments are clear.
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Figure 1. Flow chart of possible semiconductor support and expenditure structures for greater
international cooperation.
The business dynamics of the industry make it increasingly difficult for an individual IC manufacturer to justify R&D investment in new processing technology. Return on investment process equipment development (including lithography) tends to decline as the level of investment rapidly increases, although process R&D is still justified when it is closely integrated with product design.
The inevitable development of IC industries in other Asian nations creates precompetitive R&D investment problems. Although other nations may not fund basic R&D, they gain the advantage of acquiring the developed technology from international equipment and materials suppliers.
Inequality in R&D investment levels is also a result of individual companies adopting the same strategy. These free-riders (simple buyers of equipment or followers) avoid all process R&D loss by allowing others to fund all development. R&D contributors (leaders) gain intellectual property rights and immediate access to new technology with resulting benefits to production.
To solve such problems, the Japanese semiconductor industry currently has its own private consortium (Selete), in addition to a government-sponsored R&D consortium (ASET). They are effective to some degree, but are still insufficient.
The report recommends that the government of Japan should expand its current R&D projects so as to start two classes of programs for next-generation lithography: one to advance global technology and one to maintain national (Japanese) competitiveness. It will be a narrow path that advances both missions under expected budget constraints.
The former mission should be attained through research solicitations accessible to individual (US, EU, or any other) scientists and engineers in universities or national laboratories. Improved communication with organizations in the US and EU would help to integrate future international research (Fig. 1).
Polling Japanese industry
To determine Japan`s post-optical lithography research needs, ERI-KSK conducted interviews with leading research organizations. Interviewees were asked to respond to a series of questions in three parts:
Part l: What are the R&D resource needs for ArF (193 nm), x-ray proximity, and EB direct write?
Part 2: What are the major technological problems (wish-list items to be added to new research programs)?
Part 3: What are the impacts and insufficiencies of current research consortia (including ASET and any possible international organizations)?
The interview conditions were as follows:
1. Individual answers from interviewees were under nondisclosure agreements (even for MITI). Only the averages of all responses were disclosed.
2. Budgets included salaries and some per capita expenses.
3. Budgets excluded costs for real estate or construction of cleanrooms.
4. Current and future horizontal R&D alliances among chipmakers were not considered.
5. Current programs underway at ASET were not considered.
6. Chipmakers` current strategic research efforts into specific technologies were not considered.
7. EUV research costs for Part 1 (see above) were not considered.
Suggested research programs
Neither the author nor ERI-KSK is responsible for recommending specific individual research items or potential new programs to be added to the current government-sponsored R&D project, the Super-advanced Electronics Technologies Development Promotion Project of MITI (ASET is a consigned research association). The following programs, selected and compiled from the result of ERI-KSK surveys, are listed as references for discussion among the parties concerned:
l. A program to solicit research proposals from scientists or engineers (mainly in universities or national laboratories) without questioning residency could be initiated. The report recommends the following new research areas:
mask-to-wafer alignment,
high-speed data processing for e-beam direct write,
algorithms for alignment-mark detection for e-beam direct write, and
algorithms for discrimination of false and real pattern defects.
2. A second category of programs could be extensions of current ASET projects, with equipment and materials suppliers cooperating with chipmakers. The report recommends that research could include the following:
EUV,
maskmaking/inspection
epair,
resist technologies, and
improved equipment test beds.
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Figure 2. Ring diagram showing lithography market windows for future device generations.
In addition to these research areas, other post-optical lithography technologies could be investigated. With many possible directions to be explored (Fig. 2), it is certainly not possible to attempt them all. Also, since it is currently unknown which ones will be fruitful, it is difficult to define the investment level that would be required to produce a desired result. The report recommends the following research areas as feasible for domestic R&D or international cooperation:
improved sources of x-rays and e-beams (electron guns);
designs and materials for x-ray beam-line mirrors, and windows for the enlargement of the proximity exposure area;
e-beam equipment mini-environments to provide isolation from electric/magnetic fields, microcontamination, and vibration to minimize Coulomb effects; and
defect-analysis concepts.
Necessary investment levels
A chipmaker with no horizontal R&D alliances would have to spend (on average) a total of ?27 billion, starting in the current time frame (1997/98), in order to reach prototype alpha-site versions of ArF, x-ray proximity, and EB direct-write systems. A resist supplier would have to invest around ?8 billion to develop photoresists compatible with all three lithographies.
A wafer exposure equipment supplier in Japan would have to spend around ?44 billion (on average) for the same period as the above, in order to reach prototype alpha-site versions of all three technologies; this average figure is very rough because of the wide range of hypothetical investment levels reported by equipment companies.
A mask-writing (EB) equipment supplier would have to spend (on average) ?10 billion to develop both ArF (first and possibly extended generations) and x-ray proximity mask production. This figure does not include EB direct write, which doesn`t require masks. A mask-pattern-defect-inspection equipment supplier would have to invest around ?6 billion to develop resolution for 0.15-0.13-0.10 ?m design rules.
The Japanese semiconductor industry`s anticipated annual requisite R&D investment for ArF, x-ray proximity, and EB direct write (?14 billion) represents only 2-3% of current R&D investment levels in Japan (?540 billion in 1996, including product R&D). However, it is getting more and more difficult for chipmakers to invest R&D resources in such cutting-edge, precompetitive areas.
Without horizontal alliances, including ASET and/or international consortia, Japan will have to spend more than ?270 billion for all of the above three lithographies in order to reach only the prototype alpha versions:
?110 billion - Japanese IC industry,
?130 billion - Japanese equipment industry, and
?30 billion - Japanese materials industry (resists).
To accomplish the goal, more than ?35 billion/year of R&D investment would be needed for each of the next eight years leading up to 2005, divided into ?14 billion to the Japanese IC industry, and ?21 billion to the Japanese equipment and materials industry.
Even if individual horizontal R&D alliances or additional ASET programs are created, Inoue states that only minimal reductions in these investment levels can be expected. The report ignores EUV lithography research as a possibility in calculating hypothetical post-optical lithography investment requirements. Far more resources would be necessary if preliminary EUV development results are encouraging and companies decide to consider it seriously as a lithography option.
These investment levels are only the minimum anticipated requirements to develop prototype alpha-site technology. After that, IC makers and equipment and materials suppliers will have to expend far more technical resources to refine these prototypes into production-worthy tools suitable for use in a real factory
Conclusion
A new framework for international R&D cooperation may be desirable in the present era of increased worldwide standardization of core process technologies. Current R&D efforts at worldwide IC manufacturers are supported by the resources of the respective countries` national laboratories. International cooperation in critical precompetitive R&D could move forward through coordinated investment in the different counties` national labs, instead of individual national R&D "projects" like (the past) SEMATECH or (current) ASET.
If increased international R&D cooperation is desired, then the report recommends several specific changes within programs at MITI:
Vigorously solicit non-Japanese chipmakers and/or equipment and materials suppliers to join the ASET x-ray proximity program (ArF and EB direct write are Selete`s responsibilities).
Encourage collaboration between MITI, other Japanese national laboratories, chipmakers (Japanese and/or international), and equipment and materials suppliers (Japanese and/or international) to develop EUV lithography. ASET, or its following organization, could represent Japanese chipmakers. MITI should leverage the resources of Japanese national laboratories, instead of creating another national R&D project.
Make developed technology accessible to Japanese and international chipmakers and equipment/materials suppliers that do not formally join in any private R&D consortia. Access could be achieved by simple purchase, by rights to public patents (developed by national laboratories), or by purchasing developed equipment/materials. n
Acknowledgment
Japan/US/EU R&D Cooperation & Competition for Global Advancement of Technology and Regional Competitiveness (Japanese Government Policy toward R&D in Semiconductor Lithography) is copyright 1997 by ERI-KSK. Data used by permission. For more information, contact the Economic Research Institute, Kikai Shinko Kyokai, 3-5-8 Shiba-koen, Minato-ku, Tokyo 105, Japan, ph 3/3434-8236, fax 3/3434-3696.
ED KORCZYNSKI is West Coast Editor for Solid State Technology. He received his BS degree in Materials Science and Engineering from the Massachusetts Institute of Technology. He has more than 10 years of engineering and management experience in process development and equipment marketing. His current interests are thin films, process integration, and plasma and vacuum technology. He is a member of the
Materials Research Society. Solid State Technology, 1700 S. Winchester Blvd., Suite 210, Campbell, CA ph 408/370-4833, e-mail [email protected].