Technology News
10/01/1997
Japan's Super Silicon group moves toward 400-mm wafers
Even as the advent of 300-mm wafers occupies a huge share of the industry's engineering and managerial expertise, the Japanese Super Silicon Crystal Research Corp. (SSi) has been working smoothly toward the production of 400-mm (16-in.) silicon ingots and wafers.
The organization, funded jointly by Japan's government and seven major Japanese silicon producers, has applied for some 80 patents in the field over its first year of work, and expects to complete its work by early 2001 — about four years before 400-mm wafer shipments are forecast to equal today's 300-mm levels. After development work ends in 2001, the SSi will continue to exist for another 20 years as a patent management firm, collecting royalties from licensing agreements in an effort to reimburse the Japanese government for its 50.1% funding of the 13.4 billion yen (about US$115 million) program.
A formal presentation of early results is slated for next May by research center head Dr. Kiyoshi Takada, at the International Semiconductor Silicon Symposium in San Diego.
During its first year, SSi has completed a roadmap for 400-mm development (see figure), simulated the crystal-growing process and designed prototype equipment, and chosen several equipment manufacturers as development partners. The group's research facility is located on the site of Shin-Etsu Handotai's (SEH's) Isobe Plant, Gunma Prefecture; construction was completed in June, and installation of research and analysis equipment is under way. SSi is renting 6400 m2 in the 10,000-m2, three-story building from SEH until January 2001.
Slated for installation this fall is a 400-mm crystal-pulling system from Leybold Systems, which will be fitted with a large Mitsubishi Electric superconducting magnet. Next February, Tokyo Seimitsu is scheduled to deliver an ingot wire saw, while the following month is to see arrival of a two-side polishing system from Disco. One epitaxial furnace from Moore Epitaxial is already in place; Moore will design a new 400-mm version in 1998 based on results with this tool.
 SSI's roadmap for 400-mm development. (Courtesy of Wafer News) |
Also on the supplier list are Ferrofluidics and Japan Electro-Optical Ltd. (JEOL). Information on what equipment the two firms will supply was not available, but given their backgrounds, Ferrofluidics is likely to be providing crystal-growing equipment, with JEOL probably supplying characterization tools.
The technical challenges of growing 400-mm ingots and then slicing wafers out of them are daunting. As currently envisioned, the process (scheduled for achievement in January 2001) will require an ingot weighing 400 kg, four times the current industry standard, with metallic contamination of 108 atoms/cm2, two orders of magnitude better than today's wafers. Even as wafer size goes up, flatness specifications will grow more stringent — to 0.13 µm or less, compared to 0.5 µm today. Minimum particle size will be 0.04 µm, down from the current range of 0.16 µm.
Growth of such large ingots is one area where a breakthrough is needed. Others include the suspending of such a heavy crystal, and feeding silicon to the melt during growth; fabrication of a large enough quartz crucible with the necessary purity and long life; precise control of the ingot's thermal history; and safety management during crystal growth.
Market researcher Rose Associates, Los Altos, CA, notes in a recent issue of the Electronic Materials Report that Mitsubishi Materials Quartz is planning to supply 40–44-in. crucibles to SSi; 22-in. vessels are for 200-mm wafer production, and 28-in. and 32-in. units for 300 mm.
In the wafer fabrication area, researchers will be challenged by the cutting of ingots using multiwire saws, polishing the wafers without etching, and the development of single-wafer wet cleaning.
When 400-mm technology arrives, epitaxial wafers will be commonly used, so epi growth is a major part of the SSi roadmap. Growing uniform, thin, high-purity, defect-free epi layers at low temperatures is a primary challenge, as is precise control of the transition region between bulk and epi layers.
Finally, the program will push metrology beyond its current limits, calling for surface particle detection at the 0.04-µm level, new flatness measurement algorithms for the demanding flatness spec, and characterization of the wafer surface and several microns of the sub-surface region.
SSi will collaborate with the Selete 300-mm equipment evaluation consortium and the Advanced Semiconductor Equipment Technology (ASET) R&D organization, said Takada. SSi may ask Selete to evaluate 400-mm wafers by cutting them down to 300 mm. Some sort of joint program or technology exchange with ASET on wet cleaning is envisioned.
Taking part in the SSI work are the Basic Technology Research Promotion Center, an affiliate of the Japanese Ministry of International Trade and Industry, along with silicon wafer producers SEH, Sitix, Komatsu Electronic Materials, Mitsubishi Materials Silicon, Toshiba Ceramics, NSC Electron, and Showa Denko. The government had initially wanted the consortium to be international, but foreign vendors (including Wacker and MEMC) declined to participate. — P.N.D.
KLA-Tencor improves patterned wafer inspection
Since completing the industry's largest merger in May, the combined KLA-Tencor has already demonstrated signs of a strong union. The company introduced at Semicon/West the industry's first automated defect classification (ADC) matching software along with a new patterned wafer inspection tool for CMP wafers. The inspection platform combines an ultra-broadband (UBB) illumination source and significantly improved bright field optics with segmented auto thresholding (SAT).
CMP creates new and unique defect types, such as micro-scratches, residual slurry, and dishing. In conventional brightfield microscopes, nonuniform film thickness from the CMP process causes interference of the reflected light, leading to extreme color variation. In a gray scale representation, this color change translates into an intensity variation, creating process "noise" that reduces the sensitivity of the inspection systems. UBB illumination on the wafer during inspection, when combined with enhanced brightfield optics to average out intensity variations, can increase the signal-to-noise ratio for higher sensitivity to many defect types.
The process-induced noise can also be suppressed during image processing. Traditionally, images are digitized into small pixel grids, aligned, and compared for defects either die-to-die, or cell-to-repeating cell. Earlier platforms used fixed thresholds for acceptable levels of background noise (gray level difference in images) over the entire imaged area, resulting in digitized images with grainy features. Special SAT algorithms allow the new platform to segment the wafer images based on the gray level signatures of the pattern and dynamically set separate thresholds for each segment, replacing the single threshold for the entire image (see figure). The resulting images have much higher resolution as a result of the adjusted sensitivity levels for different structures.
Once defects are detected by inspection systems from KLA-Tencor or other manufacturers, they are classified into the ADC portfolio. Users can then standardize classification schemes to classify defects consistently, accurately, and quantitatively both within and between fabs. — M.Y.M.L.
Argonne Lab spinout targets cluster tool market
With plans to commercialize its aluminum vacuum technology, Argonne National Laboratory has established UHV Aluminum Co., Chicago, a new firm aimed at producing aluminum ultra-high vacuum chambers for the semiconductor equipment industry.
The 16-person operation, established in January by Argonne's ARCH Development Corp. arm, is working with cluster tool developers in its effort to develop economical aluminum vacuum applications in the thin-film deposition equipment, vacuum coating equipment, and analytical instrumentation arenas.
"In particular we believe that next generation cluster tools would benefit from our fabrication capabilities and that as the industry seeks to produce feature sizes below 0.2 µm, our low base pressure systems will serve a fundamental role in film deposition," said Glenn Tisdale, director of business development for UHV Aluminum.
Aluminum ultra-high vacuum technology was first developed as part of Argonne's Advanced Photon Source (APS) project at the University of Chicago. The technology has been used to construct the storage ring for APS's x-ray synchrotron. To date, the storage ring has been shown to operate at pressures of < 3×10-11 torr.
Traditionally, vacuum systems capable of performing at this level have been made of stainless steel and not aluminum, because steel can achieve low outgassing rates without special surface finishing and processing. In contrast, aluminum typically has high outgassing rates. Under standard manufacturing techniques, aluminum oxidizes, creating a highly porous oxide layer about 150 Å thick, resulting in systems with pressures no better than >10-8 torr.
But, despite aluminum's typically high outgassing rates, Tisdale said its ease of machining, high thermal conductivity, and low residual radioactivity make it a compelling alternative to stainless steel for certain applications, such as those being used by the APS synchrotron community and in UHV's cluster tool applications.
To overcome aluminum's high outgassing rates in ultrahigh vacuum applications, Argonne has developed a specialized manufacturing process for the material. Using specialized cutting fluids, Argonne, and now UHV, can create a highly dense oxide layer that is roughly 15–20 Å thick. Because the layer is not porous, it does not trap gas to the same extent that the porous layers did, thereby delivering outgassing rates on par with stainless steel. — Christine Lunday, WaferNews
Pall, Unit Instruments form alliance
Ultrafine filter manufacturer Pall Corp., East Hills, NY, and mass flow control (MFC) manufacturer Unit Instruments Inc. have entered a technology development alliance. The companies will work together to develop an MFC that will integrate Pall's PPT purification system and Unit's MFC into a single component for gas delivery systems. The component will retain Unit's Z-bloc design (see figure) and feature Pall's purification enhancements.
Pall's PPT purifier reduces the moisture content of process gases down to parts/trillion, essential with the advent of 300-mm platforms and 0.18-µm geometries. With a MFC that incorporates the PPT into a single component, and with the same footprint as conventional MFCs, manufacturers will be able to achieve enhanced purification without redesigning existing gas delivery systems. They will be able to upgrade their existing tools and operate in new ranges.
 Unit Instruments' Z-Bloc modular gas components simplify gas system assembly. |
According to Pall's Frank Stamatatos, introducing a purifier to a MFC will save time, as the system can be put back online more quickly. Moreover, the vertical design will save 50% space. The product is expected to be available in 6–12 months and is estimated to have a worldwide market of $15 million/year.
Meanwhile, fresh from a merger with Tylan General, Millipore launched new quick change filters, heated throttling gate valves, and all-metal mass flow controllers. The newly merged company is taking full advantage of the complementary expertise of Millipore's filtration and purification technology and Tylan's flow control, vacuum measurement, and integrated gas handling experience. At Semicon/West, Millipore showed a modular gas panel incorporating filters, purifiers, MFCs, transducers, capacitance diaphragm gauges, and gas moisture monitors. — L.S., M.Y.M.L.
Wafers metallized with copper; PVD, electroplating used in damascene process
As part of its effort to provide member companies with a head start of 6–12 months in the move to copper metallization and the use of low-k dielectric materials, Sematech's interconnect program has used a damascene PVD/electroplating process to produce a copper metal layer on wafers.
A PVD system made by Varian Thin Film Systems (now part of Novellus) and a Semitool electroplating tool were used for this round of wafers, which have a PVD barrier layer of an undisclosed material and a copper seed layer, along with the electroplated gap-fill interconnects. The Sematech interconnect lab also has CVD tools in place, and is experimenting with various processing combinations to help its member companies and toolmakers understand the pros and cons of each, said Jon Dahm, director of interconnects for the consortium.
While this round of wafers used silicon dioxide as a dielectric material, plans call for a demonstration of copper plus a low-k dielectric by the end of the year, said Dahm. By the end of 1998, the group hopes to demonstrate a dual damascene copper-and-low-k process, which should reduce the number of process steps needed for each interconnect layer by combining vertical and horizontal interconnection into a single deposition run.
Dahm said that "four or five" low-k materials are seen as "very viable candidates," but declined to name them. Vapor-deposited and spin-on materials are being evaluated. "There isn't a perfect material," he said, noting industry roadmaps suggest a "parade of materials" will arrive in the next few device generations. "It's a daunting task. The industry has never changed materials as often as it will over the next 10 years."
Although the processes will be transferred quickly to Sematech member companies to help them gain a competitive advantage, equipment companies who participate in the development will not see any restrictions on sales of their tools, said Dahm. — P.N.D.
Keithley study suggests parametrics can analyze interactions
Keithley Instruments' Semiconductor Division has conducted a two-year survey of operations within wafer fabs, and developed a series of suggestions that the company says can accelerate fab startup, ensure better quality during volume production, and help develop a structured understanding of the relationship between process variations and device performance. Parametric testers, which the company produces, are seen as an important enabler for improvement.
Principal researcher for the study was industry veteran P. Rai-Choudhury. Among the findings were that wafer misprocessing now accounts for more yield and reliability problems than contamination.
Bill Merkel, senior market development manager for Keithley, explained that as the number of processes used to fabricate wafers increases, as many as 10,000 variables (equipment parameters, process times, etc.) can affect ultimate device performance. Examples of these include etch time, time in cleaning baths, implant dose, and even subtleties like changeover of gas bottles or preventive maintenance on fab tools. An added layer is the interaction between multiple parameters.
As one example, Merkel noted, "you might have an overetch on a poly level, but also a longer Ldd, or a lower-than-normal Ldd dose. The reliability test could indicate better performance on hot carriers because the combination improves sensitivity. But, in a future lot, if the Ldd length is short or the dose is high, it could appear very bad, even though the overetch is the same."
The material will be presented at an upcoming series of seminars on process diagnostics. For more information, call Sherri Peters at 800/552-1115, or faxing 216/498-2932. — P.N.D.
Controlling the outplating of metal on Si wafers
Researchers at IMEC's Ultra Clean Processing group, Leuven, Belgium, determined that normal ambient lighting increases copper outplating in HF-clean baths. The deposition of trace amounts of copper in HF solutions during Si wafer cleaning can be drastically reduced by immersion in darkness. The addition of various amounts of chloride ions in the HF solution prevents copper deposition. These findings might demonstrate a cheap and controllable way to avoid copper contamination and might increase the lifetimes of cleaning baths.
HF-last processes have attracted a lot of interest because they typically result in very low levels of metallic compounds on the Si surface. However, trace amounts of noble metal ions (such as Ag, Au, and Cu) in the HF solution can deposit on the Si surface in an electrochemical process involving mobile charge carriers. This means that the semiconductor properties of the Si substrate influence the outplating of metals from ultra pure HF solutions.
Experiments were carried out on 150-mm p-type and n-type Si wafers that were pretreated with the IMEC clean to obtain an oxide-free surface with metal contamination below 1010 atoms/cm2. The wafers were then immersed for different amounts of time (5 to 600 sec) in a 0.5% aqueous HF solution at 19°C that was intentionally contaminated with various amounts of copper.
Surprisingly, illumination during immersion increased the copper surface concentration by at least one order of magnitude. Identical results are obtained for n-type and p-type Si wafers. When wafers are HF-immersed in darkness, copper surface contamination mostly forms a film that increases only weakly with time. However, a strong increase is observed after 15 sec when wafers are immersed under illumination. Copper ions tend to deposit preferentially at existing copper nuclei, independent of the illumination condition. The major effect of illumination is an enhanced growth rate of the copper nuclei.
The illumination effect could be explained by the creation of electron-hole pairs from absorbed photons with energies larger than the Si bandgap. These electron-hole pairs are then separated by the electric field in the space charge region, resulting in an increased surface concentration of minority carriers. This minority carrier concentration at the wafer surface assists the electrochemical corrosion process responsible for the copper deposition: the simultaneous reduction of copper ions and the local oxidation of the Si wafer surface.
The effect of chloride ions in the HF solution was investigated by adding HCl or KCl to the solution in a second series of experiments. The illumination effect is relatively unchanged below 100 ppb HCl, with at least one order of magnitude difference in copper contamination for conditions of illumination versus darkness. The illumination effect disappears for moderate chloride concentrations (> 100 ppb). High concentrations
(> 1000 ppm) suppress the copper deposition by the formation of soluble higher cuprous chloride complexes. Chloride ions thus provide a cheap and controllable way to avoid contamination by Cu when using HF solutions in cleaning technology. — E.K.
Intel to break ground in Oregon for first developmental 300-mm fab
Intel Corp. has begun site preparation for a facility near Hillsboro, OR, that will become the company's first (and in all likelihood the world's first) 300-mm volume production wafer fab. Full construction activity is to begin in the next 60–90 days, as soon as permits are received.
An Intel spokesman said no information was available on monthly wafer capacity, but indicated that it will be a "developmental" facility. These are typically in the 75,000–85,000 ft2 range, about half the size of full-blown fabs; they perfect a manufacturing process for a given design rule, which is then transferred exactly to other facilities.
The company's 0.18-µm process development is reportedly being done on 200-mm wafers, primarily at the firm's R&D facility in Hillsboro. The Intel spokesman explained this is part of Intel's policy of "stairstepping" generations of device development between two different groups, one in Oregon and one in Santa Clara, CA. The Oregon group handled 0.35-µm, while Santa Clara is finishing up the 0.25-µm process, after which the researchers there will presumably begin work on 0.13 µm. Intel currently has six fabs capable of running the 0.25-µm process, said the spokesman.
Some 300-mm pilot line work is reportedly set to take place at the Santa Clara D-2 fab. This is expected to allow the 300-mm fab in Oregon to start operations with an established process, and make possible the parallel building of pilot and production lines.
D-1C will be built in an area called Ronler Acres, where the 200-mm D-1B fab is already in operation. The site can hold up to four fabs, said the spokesman.
Subsequent fab projects at Intel will likely all be 300 mm, since the larger wafers should provide improved manufacturing economies. Currently, the company has 200-mm facilities under construction in Ireland, Israel, and Fort Worth, TX, all of which will begin work at 0.25-µm. These facilities are all sized to make them compatible with 300-mm equipment, and could be retrofitted in the future. The decision to do this, said the spokesman, will depend on market demand, factory loading, the age of a given fab, and other factors.
While many other companies have announced plans for 300-mm facilities, Intel's is the first known instance of actual building getting under way. Intel's microprocessors are among the largest high-volume devices on the market, so the company has a strong incentive to move quickly to the larger wafers, especially as it defends its turf against competitors such as AMD who are threatening its dominance in the high-value arena.
"[Intel's] foot is hard down on the throttle," commented one observer. "It's not a glory thing — they just want capacity."
Semi okays three nets
Semiconductor Equipment and Materials International has announced that it will publish a set of sensor-actuator network standards which, in an unusual move, specify competing systems from three different suppliers of the technology.
The announcement came after one of the sensor bus manufacturers, Echelon, published its own announcement saying that its product, LONWORKS, was selected "as a standard by Semi." The release was seen by some industry observers as being misleading, and raised the ire of competitors as it could be seen as giving the impression that the trade association had endorsed one company's technology over another.
In addition to LONWORKS, the Semi standards, which are expected to play a role in reducing the cost of producing inter-operable semiconductor processing equipment, specify DeviceNet and Smart Distributed System as sensor bus standards under the E54 Sensor-Actuator Network standard. Murray Bullis, VP for international standards at Semi, said his association generally will not specify a commercial technology when developing its standards, and added, "we had a few agonies about doing that." But because the commercial technologies pre-date the standards, Semi had no choice but to work with the pre-existing situation, Bullis said.
In addition, Semi notes that it makes no recommendations as to the choice of network technology, and responsibility for selection of the appropriate technology for a particular application rests with the user.
Bullis said, "We're trying not to play favorites for anybody; it's not a closed system. New [technologies] can be added," he said. "These new standards are the result of several years of intensive consensus-building effort by a team of industry experts working in the Semi International Standards Program." Generic device models for a variety of sensors and actuators are under development.
Sensor bus networks have the potential to simplify the collection of data from devices like mass flow controllers, pressure sensors, and thermocouples, and to ease the addition of a wider range of monitoring and control devices to wafer fab process tools. By providing a standardized scheme for connection and communication, they should in theory reduce the cost and improve the robustness of on-tool networking. — Christine Lunday, WaferNews