Issue



Low-k dielectric integration cost modelling


10/01/1997







Ed Korczynski, West Coast Editor

The wide variety of low-k dielectric materials and processes for ULSI interconnection were sorted to create generic process flows. Average material and equipment costs were then used as inputs to a generic cost-per-wafer (CPW) model for dielectric deposition (not including the costs of dielectric CMP, metallization, or lithography). The generic model outputs are useful for comparing specific processes.

It is currently difficult to compare the suitability of low-k dielectric interconnect materials for ULSI manufacturing, since processes and the materials themselves are still under development. Nevertheless, material and process choices need to be made in the next 12–24 months in order to meet the timelines of technology roadmaps [1].

Multiple fundamental materials properties are required for ULSI interconnect isolation, and subtleties in basic properties can dramatically change the process integration of a new material. Additional processing, such as the deposition of a capping layer or a stabilizing bake step, adds complexity and cost to complete process realization. Ultimately, integration costs will gate whether a material can even be considered as a candidate for production.

Silica-based glasses, with dielectric constant (k)~4, have been used for decades to isolate the metal lines on integrated circuits. Since the interlevel dielectric (ILD) k directly contributes to circuit delays [2], a tremendous number of organic and inorganic dielectric materials are under development [3]. Multiple deposition techniques and interconnect architectures are also under consideration.

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The two interconnect process flows are the standard (a-c) and the damascene (d-f). In the standard process, the dielectric between metal layers is deposited and vias are cut through (a), then metal is defined in the vias, and another metal layer is blanket deposited and etched to form lines and spaces (b), and finally dielectric is deposited within the layer to fill the gaps (c). In the dual damascene process, both dielectric layers are first deposited along with any needed barrier layers (d), then trenches for lines and holes for vias are patterned and etched (e), and finally metal is deposited to fill vias and trench-lines. Barrier layers are not shown, and planarization steps have been omitted for simplification.

Process integration is entirely nontrivial, with trade-offs in cost/complexity between dielectric isolation, metallization, planarization, and lithography. Advantages gained in one area generally result in disadvantages in another, and meaningful comparisons of the suitability of different materials for high-volume ULSI manufacturing are difficult. This paper discusses the definition of generic dielectric process flows, and correspondingly generic integration costs, to aid in the comparison of widely differing materials and processes.

Modelling challenges

The relative cost of dielectric formation is only one parameter to be considered in interconnect integration. The costs involved in metallization, planarization, and lithography are equally important. However, there are simply too many variables involved in complete process integration to attempt to define generic process flows for modelling. Thus, only the cost of dielectric formation is modeled here. It is hoped that the model outputs will be useful as relative references for overall integration.

To define generic —yet relevant —process flow cost models, the following steps are required:

  • define different potentially viable interconnect architectures
  • catalog the major families of low-k dielectric materials
  • establish commonalities between individual process flows
  • identify the processing equipment required for each flow
  • obtain average materials and equipment costs
  • make extensive assumptions to limit the variables
  • calculate with a modified industry-standard cost-of-ownership model.

The major interconnect process flows are the standard (metal-etch + dielectric gap-fill) and the damascene (dielectric etch + metal line-fill). In both processes, the metal via connections between layers are formed in a damascene manner (see figure on p. 123).

The interlevel dielectric (ILD) within and between metal lines has generally been CVD SiO2. Since there was usually a single technique that deposited a single material to surround metal lines, people continued to discuss the ILD as a single layer. "Gap-fill," such as that produced by a spin-on-glass (SOG) process, is considered as a sub-set of ILD.

In future device generations, the difficulty in meeting many simultaneously difficult material properties results in more complex structures. The ILD is no longer a single film or structure. For this study, the intralevel dielectric (IaLD) between lines within a given metal layer (gap-fill in the standard process) is conceptually de-coupled from the interlevel dielectric (IeLD) between metal layers (see ILD Æ IaLD + IeLD below).

Materials choices

There is a wide variety of potential low-k dielectric materials and processes for ULSI interconnection. For the purposes of this study, general categories of materials were sorted by the process used to produce the thin film (Table 1).

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SiOF, also termed fluoro-silicate glass (FSG), films can be produced by both plasma-enhanced CVD (PECVD) and high-density plasma CVD (HDP-CVD) systems. Minimal hardware modification is needed to convert a system from SiO2 to SiOF processing. SiOC films, though still somewhat new, should be producible on similar systems. α-CF, also termed fluorinated amorphous carbon (FLAC), is the newest low-k CVD film; preliminary process results show that α-CF films should be producible in standard PECVD and HPD-CVD systems, though multiple barrier and adhesion layers may need to be deposited in situ.

Despite their wide variety, spin-on dielectric (SOD) materials, including hydrogen silsesquioxane (HSQ) and xerogels (also termed "nanogels" and "nanofoams"), all use a similar process flow: spin, 2–3 single-wafer solvent evaporation bakes, and a batch furnace cross-linking cure. Thus, though they have different microstructures and material properties, they can all be considered to be within the same process family.

Parylene, though a potentially useful material, is not considered in this study because its processing is still undefined. Similarly, other still-novel processes (such as hot pressing, extrusion, and directly imageable materials) that are currently too difficult to model, were not considered here.

Process and equipment assumptions

The National Technology Roadmap for Semiconductors (NTRS) provided data concerning chip parameters for 0.18-µm devices using 200-mm wafers [1]:

  • 400-mm2 average chip size (between memory and logic),
  • 0.01 defects/cm2 for each process step, and
  • 5% fault probability (that a defect is a killer) results in 0.2% die yield loss.

Wright Williams & Kelly's TWOCOOL cost-of-ownership software package, commercialized from Sematech and compliant to Semi Standard E35, was used as the basis for calculations. Unless otherwise stated, TWOCOOL default values were used (including administrative rates such as labor and cleanroom area costs).

Defect costs were set to zero for the initial calculations to show the direct cost-per-wafer (CPW), instead of including the cost of lost die sales (which can exceed the direct processing costs for high-price dice). The cost of bad dice, as the cost to process additional wafer area, can then be added.

Since most materials under consideration are still in development, and repeatable processes have not yet been established, the following assumptions were required:

  • HDP-CVD systems will be used for IaLD in the standard process (gap-fill), with less expensive PECVD tools used for all other CVD.
  • SOD films will not require an undercoat, since recent direct-on-metal results are promising [6, 7].
  • SOD films will require an independent 1000-Å PECVD cap layer, for isolation from moisture and plasma, and for damascene etch definition [2].
  • SOD and α-CF layers will require a via treatment after etch, whether a thin deposition, a densification, or a plasma treatment.
  • Xerogels, though perhaps more difficult to control, will be processed with a standard SOD flow.
  • SOD material costs, in eventual high-volume production, will be close to current SOG cost.
  • SiOC deposition rates [4] and equipment costs will equal SiOF.
  • α-CF deposition rate will be half that of SiOF [8], with equal tool costs.

In addition to these materials-based assumptions, the following additional equipment assumptions are based on the requirements of high-volume manufacturing:

  • All equipment will meet NTRS defects, availability, etc.
  • All equipment will be bulkhead-mounted cluster tools, including track systems with integrated vertical cure furnaces.
  • An equal number of particles are added for each pass through any cluster tool.
  • Equipment and materials suppliers provided data for 0.25-µm 3:1 aspect ratio IaLD (0.18-µm generation gap-fill), 1.0-µm-thick IeLD, and 0.1-µm PECVD cap layers. Since IaLD and IeLD have been de-coupled, single- and dual-damascene have equivalent dielectric requirements; again, the main trade-offs between damascene metallization and lithography are not considered here. Also, any α-CF under- and over-coats are assumed to be deposited in situ [9], and thus do not enter into calculations.

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Within ±25%, all 200-mm wafer cluster tools (whether CVD or track + furnace) will require 6 m2 of Class-100 cleanroom area. A rough estimate of $0.50/wafer for bulk gases and equipment consumables was used. The polled suppliers stated that IaLD gap-fill precursor material costs would be within ±25%, thus justifying one calculation for all SODs. The α-CF precursor cost was assumed to be equal to that of SiOF. The SOD throughput (perhaps overly generous) assumes that the bakes and cures will not be bottlenecks within the track cluster-tool. The only remaining variables for an individual layer deposition were tool cost, throughput, and precursor (including in situ NF3 clean for CVD) material cost (Table 2).

Results

For an individual deposition, the SOD material costs dominate other inputs and result in greater costs than most CVD processes. An α-CF layer is similar in cost to SOD for IaLD gap-fill.

The outputs of the cost model can then be summed for each of the generic process flows (Table 3). The cost of any via treatment is assumed to be equal to PECVD cap deposition. Since it is doubtful that an IaLD material would be used with a lower-k IeLD, SiOF IaLD is not modeled with SOD or α-CF IeLD.

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There is a clear correlation between the number of processing steps required and the cost of the complete process sequence, regardless of the cost of the individual steps. CVD processes, despite higher equipment costs, are thus generally less expensive.

Process flows with additional steps add cost above the sum of the steps. A typical 0.2% die yield loss due to particles adds $5/wafer/step (not counting the cost of lost die sales). Thus, the direct costs will be at least twice that of the simple sums of the individual steps. Also, multitool process flows never reach optimal utilization due to capacity mismatch, so the effective throughput is lowered, and costs increase. SOD process flows require additional capping layers that result in the highest integration costs.

Conclusion

Since these results do not include the costs of CMP, metallization, or lithography, relatively less expensive dielectric processes may require more expensive overall processes. Also, the less expensive processes tend to have higher dielectric constants, so they may be disqualified by device requirements.

SODs (including Xerogels) have nearly equal processing costs; therefore, material properties and ease of integration will determine selection within the family of spin-on materials. Some SODs do not have sufficient thermal stability to be used with aluminum and tungsten metallization.

Lowering k by a certain percentage allows for a corresponding percentage reduction in the number of interconnect layers, and a corresponding cost reduction. However, higher processing costs for individual layers are only justified by significantly lower dielectric constants.

Though perhaps over-simple, it is hoped that these relative results are useful in sorting through the wide variety of potential low-k dielectrics for ULSI interconnect isolation. Since the costs for generic processes generated by this model are relatively consistent, similar process flows for specific materials can be compared to these results.

Acknowledgments

Thanks to the following for data, and/or direction: Lynn Forester (AlliedSignal), Dana Tribula (Applied Materials), Bill Coney (DNS Electronics), George Toskey (Dow Corning), Jeff Damron (Fairchild Technologies USA), Richard Gottscho (Lam Research), Wally Fry (Novellus Systems), James Banas (Semiconductor Systems), Bob Bryant (Schumacher), Somnath Nag (Texas Instruments), Dipankar Pramanik (VLSI Technology), Alan Levine (Wright Williams & Kelly).

TWOCOOL is a trademark of Wright Williams & Kelly.

This article is based on a paper originally presented in Symposium N of the Materials Research Society's Spring 1997 meeting, to be published in proceedings later this year. Contact the Materials Research Society, 506 Keystone Drive, Warrendale, PA 15086, ph 412/779-3003, fax 412/779-8313.

References

  1. The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1994.
  2. T. Seidel, B. Zhao, Mater. Res. Soc. Symp. Proc., Vol. 427, pp. 3–16, 1996.
  3. B. Zhao, et al., Mater. Res. Soc. Symp. Proc., Vol. 427, pp. 415–426, 1996.
  4. G. Sugahara, et al., Proc. of Dielectrics for ULSI Multilevel Interconnection Conference, pp. 19–25, 1997.
  5. T. Ramos, et al., Proc. of Dielectrics for ULSI Multilevel Interconnection Conference, pp. 106–113, 1997.
  6. M. K. Jain, et al., Proc. of VLSI Multilevel Interconnection Conference, pp. 23–27, 1996.
  7. V. McGahay, et al., Proc. of VLSI Multilevel Interconnection Conference, pp. 116–118, 1996.
  8. S. Robles, et al., Proc. of Dielectrics for ULSI Multilevel Interconnection Conference, pp. 26–33, 1997.
  9. Y. Matsubara, et al., Technical Digest of International Electron Devices Meeting, p. 369, 1996.

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Ed Korczynski is West Coast Editor for Solid State Technology. He received his BS degree in Materials Science and Engineering from the Massachusetts Institute of Technology. He has more than ten years of engineering and management experience in process development and equipment marketing. His current interests are thin films, process integration, and plasma and vacuum technology. He is a member of the Materials Research Society. Solid State Technology, 1700 S. Winchester Boulevard, Suite 210, Campbell, CA 95008; ph 408/370-4833, e-mail [email protected].

ILD -> IaLD + IeLD

Interlevel dielectric (ILD) is commonly understood as the dielectric isolation both between layers and within an individual layer of conducting lines. The dielectric within an individual layer is sometimes known as the "gap-fill."

Some companies use the term "intermetal dielectric" (IMD) to signify the insulator between and within metal lines, reserving ILD to signify the insulator associated with polysilicon conducting lines. IMD then is a subset of ILD.

Further complications in terminology arise as more complicated processes and final structures are developed to satisfy the increasingly difficult interconnect requirements of sub-0.25-µm devices.


Since interlayer dielectric (ILD) now occurs as two separate layers, the term is divided into interlevel dielectric (IeLD) —between conductor layers —and intralevel dielectric (IaLD) —within a given conductor layer.
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For example, one of the main material property trade-offs in dielectrics is that as the dielectric constant (k) is lowered (highly desirable to reduce delays in high-speed circuits), the thermal conductivity is also lowered (very undesirable since high-speed circuits generate heat that needs to be dissipated). Since the dielectric between lines in a given layer doesn't affect the thermal dissipation as much as the time delay, an obvious compromise is the use of a lower k material within a line and a slightly higher k material between lines.

With standard interconnect process flows, the material within a given metal level can properly be termed "gap-fill," since the metal lines are defined before dielectric is deposited to fill in the gaps. However, though the final interconnect structure looks similar with damascene processing, it would be very confusing to use the same term for the same dielectric within a metal layer.

Since there are numerous reasons to select two different materials for use within and between layers, and since process flows for the two materials may be relatively independent, it is now simpler conceptually to de-couple the two portions of ILD. The interlevel dielectric (IeLD) now refers to that between conducting layers (the via level), while the intralevel dielectric (IaLD) refers to that between lines within a given conducting layer (see figure).