Integration of ferroelectric nonvolatile memories

10/01/1997

Robert E. Jones, Jr., Motorola, Austin, Texas

Ferroelectric nonvolatile memories are especially attractive because of their low-voltage, high-speed write. Although these memories use multicomponent metal oxide ferroelectrics and oxygen-tolerant electrode materials that are nonstandard in Si CMOS processing, the deposition and etch techniques are related to conventional processes. Integration of ferroelectric capacitors into a CMOS process flow introduces several challenges, including process damage to the ferroelectric capacitors and interface reactions between electrode materials and conventional circuit elements.

Figure 1. Polarization vs. voltage hysteresis loop of an SrBi2Ta2O9 (SBT) ferroelectric capacitor. The difference between the logic "0" and logic "1" states is called the nonvolatile polarization (Pnv). This differs from the 2Pr determined from a dynamic hysteresis loop because of polarization relaxation.Click here to enlarge image

Ferroelectrics have a crystal structure with a remanent polarization or asymmetric charge distribution in zero field. A sufficiently large electric field can alter the direction of this polarization, providing the basis for a memory device. A ferroelectric capacitor demonstrates a hysteresis loop (Fig. 1), and the two remanent polarization states can be taken to represent binary logic states.

Figure 2. Basic memory array and sensing scheme for a FeRAM.Click here to enlarge image

In the 1950s, researchers attempted to use arrays of ferroelectric capacitors at the cross points of row and column conductors [1]. However, these did not prove practical because writing data to a specific capacitor disturbed the polarization in other capacitors. Incorporating an access transistor for each bit capacitor [2] resolves this problem (Fig. 2). In Fig. 2, all bits along a row are read or written at the same time. Either remanent polarization state can be written into a capacitor by transitioning the drive line during the write. The stored data is read by forcing the capacitor to the saturated state "S." When a logic "1" capacitor is taken to "S," a relatively large charge flow to the bit line occurs, compared to when a logic "0" capacitor is taken to "S." During the sensing operation of the read, the bit lines are taken to a "low" or "high" state; transitioning the drive line restores the data. Most designs today use a 2 transistor-2 capacitor bit cell and store complementary data in the capacitors to make the sensing operation more robust.

Figure 3. Comparison of FeRAM bit cell process architectures with a) strapped contacts and b) stacked contacts. Normally, the plate line extends to a number of capacitors, so that only occasional interconnect contacts to the plate line are needed, and these can occur outside of the bit cell.Click here to enlarge image

In comparison with conventional floating gate nonvolatile memories such as electrically erasable programmable read only memory (EEPROM) and flash EEPROM, ferroelectric random access memories (FeRAM) operate at standard supply voltages (3–5 V), have a high write speed (ª100 nsec), and provide direct data overwrite. The major challenges to widespread commercialization of FeRAMs are successful and cost effective integration with established Si CMOS technologies and demonstration of reliability. The integration must be accomplished without compromising the characteristics of either the CMOS transistors or the ferroelectric capacitors.

Process integration architecture

A ferroelectric capacitor module is introduced into the CMOS process flow after completion of the transistors and prior to interconnect metallization. This location is logical since the processing temperatures of ferroelectric capacitors are typically below transistor process temperatures (900–1000°C) and above metal interconnect temperature capabilities (max. of about 450°C for the usual aluminum-based interconnect). The numerous integration variations can be grouped into two major categories: strapped and stacked capacitor architectures. The strapped architecture (Fig. 3a) locates the ferroelectric capacitor over field oxide, and makes contacts to both the electrodes with overlying metal interconnect. The stacked architecture (Fig. 3b) connects the bottom electrode to the storage node of the access transistor through a contact plug. This design improves layout efficiency by a factor of two compared to the strapped architecture, but introduces additional materials issues.

Ferroelectric materials and processes

The most extensively explored ferroelectric materials for FeRAMs are PbZr_1-xT_xO₃ (PZT), which has a perovskite structure, and SrBi₂Ta₂O₉ (SBT), which has a layered perovskite structure (Fig. 4). Both structures have a relatively small metal cation located within an oxygen octahedron. Above their Curie temperature, T_c, ferroelectric materials have a symmetric lattice with no remanent polarization, and are said to be in the paraelectric state. Below the Curie temperature, the lattice distorts to give a net polarization (Fig. 4c). This lattice distortion is a cooperative phenomena, with neighboring unit cells having the same distortion over a region known as a domain. An applied electric field alters the net polarization in a capacitor via the motion of domain walls or nucleation and growth of new domains. For memory applications, PZT offers higher remanent polarization, while SBT has demonstrated higher endurance in electrical cycling and better scaling to thin films for low-voltage operation.

Figure 4. Crystal structure of ferroelectric materials: a) perovskite structure of PZT; b) layered perovskite structure of SBT; and c) distortion of the perovskite structure for PbTiO3 in the ferroelectric phase.Click here to enlarge image

Both of these materials require relatively high processing temperatures to achieve the desired crystal structure. The formation of the ferroelectric phase depends on the availability of oxygen, and excessive oxygen vacancies can degrade the electrical performance. Thus, these high-temperature processes usually use an oxygen-containing environment to keep the ferroelectric film fully oxidized. Ferroelectric deposition methods include spin-coat, sputtering, and CVD.

Figure 5. Scanning electron microscope (SEM) micrographs showing a) the typical columnar grains of PZT, and b) the spheroidal grain structure of SBT ferroelectric thin films.Click here to enlarge image

The spin-coat and fire solution chemistry deposition process [3] is similar to the familiar spin-on-glass. The deposition solution is spun on to the wafer, then heated to 200–400°C to remove most of the organics. Multiple coats are generally required to achieve the desired final thickness. Firing in an oxygen-containing atmosphere — after each individual coat or after all coats — produces the desired crystal structure. PZT requires crystallization temperatures of 550–650°C; higher temperatures of 750–800°C have been used for SBT. Figure 5 shows the grain structures for PZT and SBT formed on Pt by solution deposition chemistry. Figure 6 compares the hysteresis loops for PZT and SBT optimized for 3-V operation. For both materials, the phase sequence is from amorphous to an intermediate fluorite phase, and subsequently, to the desired perovskite. Excess Pb or Bi is usually added to the solution because of the loss of Pb from PZT and Bi from SBT during thermal processes.

Figure 6. Comparison of PZT (150 nm) and SBT (200 nm) hysteresis loops. The thicknesses of both ferroelectrics were tailored for 3-V operation.Click here to enlarge image

Solution chemistry approaches include sol-gel and metal organic decomposition (MOD). The sol-gel approach reacts alkoxide precursors in 2-methoxyethanol, using hydrolysis to initiate metal-oxygen-metal bond formation. This approach is water sensitive so solution stability is a concern.

MOD dissolves carboxylate or b-diketonate precursors in a solvent such as xylene. The solution is relatively stable but can require higher-temperature processes to remove the organic components. A related deposition method with improved conformality ultrasonically generates an MOD aerosol in a subatmospheric reaction chamber, then applies post-deposition thermal treatment. Advantages of spin-coat deposition include ease of composition variation and relatively low capital costs. Limitations include the planarizing behavior, particle formation, and solution aging.

Physical vapor deposition (PVD) is another common technique for deposition of ferroelectric thin films [4]. Examples include laser ablation, on-axis and off-axis sputtering, and ion beam sputtering from either single or multiple targets. While multitarget techniques are useful for rapid experimentation, RF magnetron sputtering from a single ceramic target is the more production-worthy PVD method. Sputtering often mixes Ar and O2 gases to provide an oxidizing ambient. The substrate is generally heated during deposition.

Post-deposition anneals in O₂ or N₂ may be used; experiments have successfully employed both furnace and rapid thermal annealing processes. In films sputtered at low temperature, the phase sequence on annealing is similar to that observed for solution deposition. The phase evolution can be abbreviated in films deposited at an elevated temperature, however. Sputtering processes are familiar to CMOS fabs, but poor flexibility in target composition during the development stage limits their appeal.

Metal organic chemical vapor deposition (MOCVD) is interesting for deposition of multicomponent metal oxides because of its potential for good step coverage. Both PZT [5] and SBT [6] have been deposited. Major challenges include availability of appropriate precursors, source delivery, and reactor design. Many of the available precursors have low volatility, so vapor phase delivery can require elevated temperatures. Thus, precursor degradation or modification within the heated source can sometimes be a problem. The stable temperature range for the vapor is sometimes only a little above the temperature required for volatilization.

Thermal degradation can be an especially significant problem in multicomponent metal oxide deposition as the stable vapor temperature ranges of the various precursors may not overlap. An alternative source method, flash evaporation of dissolved precursors, promises to solve many of these difficulties. Equipment vendors are making serious efforts to develop production-quality tools for these processes.

Electrode/barrier materials and processes

The high-temperature, oxygen atmosphere processing of the ferroelectric film places stringent materials requirements on the bottom electrode. Even a thin dielectric interface can drastically impact the capacitor properties because of the series capacitance effect. One solution uses an oxidation-resistant metal electrode. Another solution is to use a metal that forms a highly conductive oxide, or to use the conductive oxide itself as the electrode material.

Pt, extensively used as an oxygen-resistant electrode, has several technical disadvantages in addition to the cost penalty. First, it has poor adhesion to SiO₂ and silicon nitride, the commonly used interlevel dielectrics (ILD) in CMOS integration. Ti has been frequently used as an adhesion layer for Pt electrodes, but interdiffusion between Pt and Ti can degrade capacitor properties. Since the Ti atoms appear to remain in place if they are oxidized [7], oxidizing the Ti to rutile TiO₂ prior to deposition of the Pt layer can generate a stable system. Pb and Bi may also diffuse into Pt electrodes from the ferroelectric films. Finally, PZT capacitors with Pt electrodes exhibit early fatigue (i.e., loss of switchable polarization with electrical cycling).

Metal oxide electrodes sometimes significantly modify ferroelectric capacitor properties. RuO₂ electrodes improve the fatigue resistance of PZT capacitors in many cases, but generally increase the leakage currents. Annealing the RuO₂ bottom electrode prior to deposition of the PZT [8] or using a Pt layer on top of the RuO₂ reduces the leakage currents [9]. IrO₂ electrodes and combinations with Ir and Pt layers have also reduced PZT fatigue [10]. Various conductive multicomponent metal oxides, including SrRuO₃ and YBa₂Cu₃O₇, have also been explored as electrodes [11, 12]. While the performance of these multicomponent metal oxides has generally been good, they add process complexity.

A plug material such as polycrystalline Si that is common in CMOS technology is highly desirable for the higher-density, stacked capacitor structure. The plug material must not oxidize or react excessively with the bottom electrode during the processing of the ferroelectric film. If a Pt electrode were placed over a poly-Si plug, both silicidation and silicon oxidation would occur. Conventional diffusion barriers such as TiN and TaN have been used. Because oxygen diffuses rapidly through Pt, however, oxidation of the diffusion barrier can limit the thermal budget. Researchers have proposed the conductive metal oxides, their base metals, or combination layers as barriers as well. Appropriate electrode/barrier/plug combinations are the subject of much research.

The electrode materials can also react with the interconnect metallization. For example, Pt electrodes and Al-based interconnects will react at temperatures as low as 200°C. Fortunately, the typical TiN diffusion barrier can also act as a barrier between electrodes and interconnect.

Regardless of the electrode and barrier materials, DC magnetron sputtering is the deposition method of choice, with reactive sputtering often used for deposition of the metal oxides.

Capacitor patterning

Standard IC etch practice uses F- and Cl-containing plasma etch chemistries. The fluorides and chlorides of heavy metal constituents typically have low volatility near room temperature. Etching at wafer temperatures >200°C, however, requires hard masks due to photoresist temperature limitations. These constituents thus require a highly physical etch. The extreme case, Ar ion milling, is totally physical. Physical etching has the advantage of etching anything, with the associated problem of limited etch selectivity.

Nonvolatile etch by-products tend to coat the sidewalls of the resist and capacitor. Incident ion beam angle and resist sidewall shape modification can control sidewall redeposition, but these techniques become less successful as lateral dimensions shrink and aspect ratios increase. Using a reactive gas in the ion gun source (reactive ion beam etching or RIBE) or introducing a reactive gas such as Cl directly into the etch chamber (chemically assisted ion beam etching) adds some chemical aspect to ion milling. RIBE has had some success in improving etching of PZT, SBT, and Pt.

Reactive ion etching (RIE), operating in a highly physical regime, has been successfully applied to ferroelectric capacitor patterning [13]. Some of the lighter metal constituents of ferroelectric films (e.g., Ti and Ta) will form volatile RIE by-products. Still, many of the heavy metal components of both the ferroelectric and electrode layers form low-volatility etch by-products that can cause sidewall redeposition problems. One approach uses an etch chemistry that actually erodes the resist. Under appropriate conditions, the etching rate of capacitor materials on the resulting tapered resist sidewall can exceed the by-product deposition rate so no net deposition occurs. Etching of RuO₂ electrodes typically uses hard masks because both RuO₂ and photoresist etch readily in an oxygen plasma.

Etching of ferroelectric capacitors can cause voltage shifts or other degradation of the hysteresis loop due to charging effects during the etch. Annealing is often successful in reversing this damage. Etching can also damage the capacitor edge through chemical modification of the sidewall region or deposition of low-volatility etch by-products. Such effects may enhance leakage in the perimeter region or degrade the ferroelectric properties in this region. Unless resolved, such edge effects could limit the scalability of FeRAM technology.

Environmental, safety, and health

As with any new technology, the environmental, safety, and health aspects must be appropriately handled. Many of the heavy metals used in ferroelectric films and electrodes have some level of toxicity. Pb is well known as a toxic metal, and its use is under consideration for additional restrictions in Europe. Additionally, the precursors and solvents used for solution deposition chemistry and MOCVD must meet all environmental and safety requirements. The US EPA's Toxic Substances Control Act (TSCA) requires, with minor exceptions, that each chemical substance be listed on the TSCA inventory before it can be used in manufacturing. Some MOCVD and solution deposition precursors are not TSCA listed. The use of tetraethyl lead, sometimes reported for PZT MOCVD, is highly restricted in the US. Additionally, methoxyethanol, used in sol-gel chemistry, is a suspected teratogen and US semiconductor manufacturers have voluntarily phased out its use. Xylene solvents commonly used in MOD are US EPA Hazardous Air Pollutants and are on an EPA voluntary phaseout list.

Figure 7. Pnv vs. voltage for an SBT capacitor showing the process damage from deposition of a CLD and etch of contact openings, and the recovery of polarization properties following an anneal. Click here to enlarge image

Reactor by-products must also be considered, especially in etch chambers. For example, oxygen plasma etching of Ru or RuO₂ generates RuO₄,which is toxic, as are the chlorides and fluorides of some heavy metals. The research literature on ferroelectrics is a limited guide to appropriate action for manufacturing as different regulations may be in effect for research and in other geographical locations.

Balance of process

Following capacitor fabrication, the interconnection must be formed without damage to the ferroelectric properties. A capacitor-level dielectric (CLD) is deposited over the completed capacitors. Contact openings cut through the CLD to underlying circuit elements, including the capacitor electrodes. The CLD is typically deposited by plasma-enhanced chemical vapor deposition using SiH₄ or TEOS as the silicon source while the wafer is heated to 300–400°C. The contact etch often uses a CHF₃ plasma chemistry. These processes expose the capacitors to a hydrogen environment, and hydrogen reduction of the oxide ferroelectric is one of the most fundamental issues in FeRAM integration. Even at temperatures as low as 200°C, brief exposure to hydrogen can damage PZT films [14]. Figure 7 shows extensive damage to SBT properties following CLD deposition and contact etch. Fortunately, an oxygen anneal can recover this damage. Charging effects during deposition and etching of the interconnect metal layers can damage the ferroelectric capacitors, but appropriate process optimization can resolve these problems. The deposition of the ILD and the final passivation dielectric again raise the hydrogen problem. For instance, standard CMOS process integration uses a forming gas anneal to passivate gate oxide interface states after final metal patterning. Figure 8 shows a cross section through a completed FeRAM bit cell.

Figure 8. SEM micrograph of a cross section through a FeRAM bit cell.Click here to enlarge image

Ferroelectric materials are also piezoelectric. Mechanical stresses imposed by the substrate, the electrodes, the overlying dielectric and metals layers, and even by the IC package can significantly alter the ferroelectric properties. For example, lattice mismatch strain can raise the Curie temperature in epitaxial barium strontium titanate as much as 400°C [15]. Another significant integration concern is that ferroelectric capacitor heavy metals may reach the transistors and potentially degrade them. Appropriate protocols must be in place to avoid cross contamination of other processes. The successful processing of FeRAM circuits shows that solutions exist, but these integration details are generally considered proprietary so there is little information in the literature.

Reliability

There are several important FeRAM reliability considerations [16]. The loss of nonvolatile polarization (P_nv) with bipolar electrical cycling, known as fatigue, has been a major problem with Pt-electroded PZT capacitors. Metal oxide electrodes with PZT have made some progress. SBT, on the other hand, has good resistance to fatigue even with Pt electrodes. Accelerated tests at elevated temperature or operating voltage show SBT to be resistant to fatigue at normal 3-V operation to at least 10¹² cycles at temperatures as high as 125°C (Fig. 9) [17]. At 175°C, however, the onset of fatigue occurs after 10¹¹ cycles.

Figure 9. Reliability of SBT against fatigue as a function of the test temperature.Click here to enlarge image

Retention loss, the loss of stored data with time after writing, is another important reliability factor. Increased temperature can accelerate retention studies, but increased write voltage cannot: higher write voltages may actually reduce retention loss.

Imprint, the loss of the ability to switch a ferroelectric capacitor to the opposite state either for a write or a read operation, is a third significant reliability issue. Imprint can result from voltage shifts in the hysteresis loop. It depends on both thermal and electrical history in a complex way, and standardized testing methodologies have not yet been established. The mechanism for imprint may be electron trapping in the interface region of the ferroelectric, and this trapping may be enhanced by alignment of oxygen vacancy-containing defect dipoles [16].

Summary

FeRAMs with strapped capacitors and 2 transistor-2 capacitor bit cell architecture have been in limited commercial production for several years with CMOS technologies in the 0.8–1.2 µm design rule range. The key to a larger market for FeRAM applications is resolution of the integration and reliability issues for higher-density technologies.

Acknowledgment

The author thanks his many colleagues at Motorola in the ferroelectric development effort, and especially Peter Zurcher, Papu Maniar, Peir Chu, Bo Jiang, Sufi Zafar, Joyce Witowski, Bruce White, Deborah Taylor, C. Sudhama, Reza Moazzami, Andy Campbell, Tom Lii, Laurie Beu, Joe Mogab, Brad Melnick, and Sherry Gillespie.

References

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Click here to enlarge image

Robert E. Jones, Jr. received his PhD degree in solid state physics from Iowa State University. He is currently manager of advanced materials for embedded memories in the Materials Research and Strategic Technologies Laboratory at Motorola, which develops ferroelectric technologies for memory applications. Motorola, Advanced Materials Group, Materials Research and Strategic Technologies, MD K-10, 3501 Ed Bluestein Blvd., Austin, TX 78721; ph 512/933-7237, fax 512/933-5497.