300-mm premetal dielectric processing
09/01/1997
300-mm premetal dielectric processing
W.J. Schaffer, Watkins Johnson, D. Schey, IPEC Planar, M.L. Bowman, I300I
W.A. McGahan, Nanometrics Inc., J.K. Boisen, Moore Technologies Inc.
Y.E. Strausser, Digital Instruments Inc., M.E. Bran, Verteq Inc.
The net manufacturing cost of silicon die dominates the economics of IC fabrication. The industry relentlessly pursues robust, massively parallel fabrication processes to drive the die cost down. Historically, the number of die/wafer pass is increased by reducing transistor critical dimensions or by introducing larger starting wafers into the fab line. The latter approach is more dramatic, unless the costs of new capital equipment and process development consume the cost advantage of additional silicon area. The present article reports tool performance results for a first pass effort at 300-mm premetal dielectric (PMD) processing, including data for RTP densification of BPSG and for materials-related aspects of oxide chemical mechanical polishing (CMP). The closing remarks discuss the role of informal collaboration in 300-mm tool development.
Currently, the semiconductor industry is laying the financial and technological foundations for 300-mm wafer processing [1-3]. Wholesale replacement of the existing toolset will be expensive and there is significant debate about distribution of this financial burden between chipmakers and equipment suppliers. Although some chipmakers have announced plans to begin 300-mm pilot processing as early as the first half of 1998, it is not entirely clear when volume purchases of 300-mm equipment will be made. Equipment suppliers are reluctant to invest in significant development programs solely for the early adopters. If made too early in the product life cycle, capital and resource allocations for 300-mm equipment development will not match the return from other investments. Consortia in the US, Japan and Europe (I300I, SELETE, SEMI, J300, JESSI) are helping to resolve 300-mm processing issues and streamline the development of standards and equipment.
Although the window for volume sales is not well established and focused development programs are uncommon, equipment suppliers seem to have universally addressed the 300-mm market. Either by virtue of forward compatibility, prototype development, or dedicated R&D programs, 300-mm capability is available for most IC processes. Short loop process integration demonstrations are possible and a few have been performed privately, though not widely reported.
During 1996, just prior to the current explosion of interest in 300-mm process development, the noncompeting companies listed on this page agreed to address informally some of the 300-mm development issues. We used a short loop PMD process (oxide deposition, densification, metrology, planarization, cleaning, and characterization) to achieve more general goals:
accumulate 300-mm process experience,
benchmark the current performance of existing equipment,
verify that 200-mm techniques are suitable for 300-mm wafers,
add to materials knowledge for RTP and CMP of deposited oxides,
publish an example of a 300-mm short loop process,
informally share market requirements information, and
explore informal collaborations as a means of reducing individual development costs for 300-mm tools.
Figure 1 shows a flow chart of the experiment. The design mimics the low-thermal-budget, single-wafer processing scenario anticipated for 300-mm wafers at 0.25-0.18-?m linewidths.
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Figure 1. Flowchart for the 300-mm premetal dielectric experiment. The PMD process is described by the column of boxes in the center of the figure; the "inputs" to the process are shown on the left; and the characterization methodology is shown by the column of boxes on the right. The measured performance parameters are shown as outputs of the characterization steps.
Wafer acquisition
Approximately half of the 22 unpatterned test wafers used in this experiment were acquired through the I300I wafer loan program. A commercial vendor supplied the balance, advertised as "prime" in the first quarter of 1996. The limited information provided with these wafers (bow, warp, total thickness variation, p-type doping level and uniformity, and etch pit density) was consistent with "prime" for the current 200-mm generation.
BPSG deposition by APCVD
Dielectric deposition by APCVD will persist in sub-0.25-?m, 300-mm applications, due to the excellent gap filling characteristics of TEOS:O3 chemistry. We investigated four B/P compositions:
1. undoped glass (SiO2) for trench isolation oxide,
2. 2/4wt% BPSG as a low densification temperature glass,
3. 4/4wt% BPSG as a moderate flow glass, and
4. 0/6wt% PSG for nonflow gettering and etch applications.
We deposited 1.5-?m-thick films at 500? in a manually loaded APCVD system. The linear injectors in this tool are designed to deposit BPSG onto two 150-mm wafers in parallel using TEOS/O3 chemistry and customary dopants (TMB and TMPi). Deposition onto 300-mm wafers requires only minor modifications. Neither the temperature profile nor the gas flow conditions were optimized for 300-mm wafers prior to this work. X-ray fluorescence measurements [4] of 200-mm wafers interspersed into the experiment verified dopant concentrations.
The linear injector design appears to have a scalability advantage over showerhead CVD technologies since the deposition zone has only one symmetry plane. Thus, the deposition chemistry is independent of wafer diameter (injector length) and can be scaled to arbitrary sizes. For example, APCVD is currently used in flat panel display manufacturing.
Thickness metrology
The as-deposited film thickness uniformity (sample standard deviation/sample mean) contributes to planarization rate uniformity. In this work, thickness distributions were measured with a fully automated absolute visible reflectometry (400-800 nm) mapping system [5]. The fundamental spatial frequency of variations is low (0.05 mm-1) in most CVD (and CMP) systems, so 121-point maps (5 concentric radii) can determine thickness variations. Diameter scans (100 points) correspond more closely to die spacings. Edge bead scans (50 points within 20 mm of the wafer edge) reveal edge exclusion performance, especially important for CMP tool development.
Figure 2 is a 121-point thickness uniformity map for an as-deposited B/P = 2/4wt % APCVD BPSG film. The edge thick deposition shown is common to all the APCVD films in this experiment. The 1s uniformity is 2.5%, the best obtained in this experiment. The undoped films are the least uniform films (4.2% max.). Subsequent development on undoped films reduced the as-deposited uniformity to <1.9%. For comparison, uniformities of wet thermal oxide films (seven were used for CMP removal rate normalization) range from 0.9% to 1.9%.
Metrology tools are conceptually the easiest to scale for larger-wafer diameters. Wafer positioning, handling, ergonomics, software, and throughput will differentiate among the available tools, especially for "point" measurements like reflectometry.
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Figure 2. As-deposited thickness uniformity map for 2/4wt % BPSG film deposited by APCVD.
Densification by RTP
Stress hysteresis and FTIR studies typically report higher hydrogen (moisture/silanol) concentrations and lower film densities for APCVD BPSG films than for thermally grown oxides [6]. Further, the film stress of APCVD oxides on silicon at room temperature is usually tensile, rather than the compressive stress found in thermal oxides. The as-deposited film properties depend on several parameters, e.g., the TEOS:O3 decomposition chemistry at the deposition temperature, the B/P dopant level, dopant precursors, relative and absolute flow rates, and so on.
Annealing, either in a furnace (typically 30 min.) or by RTP (typically 30-60 sec), drives as-deposited APCVD oxide properties toward those of thermal oxide. Understanding of BPSG densification and flow by furnace annealing is fairly complete. To determine appropriate densification temperatures for RTP, however, we performed a pilot experiment with 200-mm wafers.
Figure 3 compares the room temperature stress as a function of maximum anneal temperature for both furnace (30 min.) and RTP (60 sec) annealing of a 2/4wt % film [7]. Similar data is obtained for the other B/P doping levels. Either annealing method reaches the equilibrium compressive stress near the glass transition temperature (Tg = 725?C for a 2/4wt% BPSG film) [8]. However, the saturation compressive stress of the film processed by RTP is 35% higher than that obtained by furnace annealing. The local structure and/or chemistry for the RTP annealed film differs, therefore, from the furnace annealed film.
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Figure 3. Comparison of evolution of biaxial stress after furnace and RTP annealing.
If a film annealed for 60 sec by RTP at TA>Tg is later annealed for 30 min in a furnace at TA>Tg, it will relax to the less compressive furnace stress value. Apparently, the structural rearrangements involved in the conversion from tensile to compressive stress involve short-range, atomic-scale modifications to the ring structure of the glass. The longer time to obtain the minimum compressive stress (-125 to -90 MPa) is, however, reminiscent of diffusion processes and may correspond to silanol recombination and subsequent outdiffusion through the film surface.
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Densification of the 300-mm wafers, performed in a RTCVD system [9] for 60 sec, used the temperatures given in Table 1. The wafers were robotically loaded onto a SiC-coated graphite susceptor that can accommodate wafer sizes up to 400 mm. The lamp
eflector assembly provided a maximum ramp rate of 25?C/sec.
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Densification of APCVD films appears to decrease the film thickness, as measured by reflectometry (Table 2). The shape of the distribution was preserved, suggesting that the densification is homogeneous and localized under these anneal conditions. The film thicknesses of RTP-annealed films are statistically indistinguishable from furnace-annealed ones.
The full range of applications of atmospheric and subatmospheric pressure CVD (APCVD/SACVD) techniques at 300 mm will be determined in part by the ability to densify the deposited glass. As the critical dimension shrinks, the allowed thermal budget after well/junction formation and salicidation shrinks as well. RTP reduces the thermal budget for densification by a factor of 30.
Planarization
CMP is expected to be the planarization method of choice for the foreseeable future. Both metal and oxide CMP must provide a fast planarization rate that is uniform from die to die and wafer to wafer. Stable platforms, long-lived pads, and uniform slurry distribution for large wafers pose considerable engineering problems.
In our studies, CMP is performed on a manually loaded orbital polisher. Since uniformly patterned 300-mm wafers are difficult to obtain, the study compared CMP removal rates and uniformities for blanket films of the four BPSG compositions to prior results. Seven additional wet thermal oxide wafers were included in the lot at this point to obtain normalized removal rates.
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The polishing parameters (Table 3) were constant for all wafers. Since the CMP removal rate increases quadratically with B/P doping, these parameters are aggressive for B/P = 4/4wt % films but not for thermal or undoped APCVD oxides.
Table 3 describes the pad preparation as "partially grooved:" the area of the pad that is grooved for slurry distribution is less than that covered by the orbital motion of the planarizer (a tooling limitation). Since the pad is not prepared uniformly over the entire polishing area, the slurry distribution is different for diameters >200 mm. This variation accounts for the significantly different polish rate observed at the wafer edge.
Figure 4 compares the post-anneal and post-CMP 121-point thickness maps (6-mm edge exclusion) for a 2/4wt % BPSG film. The average removal rate for this film is 1410 ?/min and the within-wafer uniformity is 11.5%. The low removal rate at the periphery and high nonuniformity are due to the nonuniform slurry distribution effect described above. The interaction between the initial edge-thick character of the deposited oxide and the low peripheral removal rate degrades the uniformity over the full 300-mm diameter. The uniformity in the inner 200 mm of the 300-mm wafer, where the polish conditions are homogeneous, is 5.1% and is comparable to previous results on 200-mm wafers [10].
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Figure 4. 300-mm thickness difference map for 2/4wt % BPSG.
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Figure 5. Oxide CMP removal rates for all APCVD and thermal oxide films. The large range bars arise from large variations in the rate observed in the outer 25 mm of the wafers, caused by nonuniform slurry distribution at the periphery.
Figure 5 shows the removal rates for all wafers, calculated from full 121-point maps (300 mm). While within-wafer nonuniformity is high for the the full 300-mm difference map, the nonuniformity calculated for the inner 200 mm is comparable to previous results (Fig. 6). Slower polishing of the periphery due to slurry starvation accounts entirely for the difference. The average 1s nonuniformity for all thermal oxide films (18.6%) is nearly identical to that for APCVD films (18.7%). Removed layer nonuniformity due to B/P doping is not apparent.
Figure 7 compares the dopant dependence of the average normalized removal rate (data in Fig. 5) for higher compressive stress RTP-densified films (current results) and for lower compressive stress furnace-densified films (prior results) [10, 11]. The higher stress observed in the films densified by RTP lowers the removal rate. Scaling the coefficients of the chemical terms by the fractional deviation from equilibrium stress gives a good fit to the current result from the prior model. This plot separates the independent effects of dopant composition and film stress on removal rate.
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Figure 6. The effect of nonuniform slurry distribution near the edge of the 300-mm wafers on the observed nonuniformity of the removed layer is demonstrated by comparing the results using the full 300-mm diameter (open circles) to those from only the inner 200 mm (filled circles).
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Figure 7. Comparison of normalized removal rate for furnace-densified vs. RTP-densified APCVD films. The RTP densified films have 35% higher compressive stress, which lowers the removal rate.
Uniform global planarization for 0.25-?m lithography is critical throughout the process flow (e.g., isolation, PMD, interconnect). Reasonably uniform CMP results can be obtained on 300-mm wafers even under less than optimal planarization conditions. Uniform slurry distribution is required before other effects (e.g., nonuniform wafer stress during planarization) can be investigated systematically.
Post-planarization cleaning
Subsequent tungsten contact lithography and fill steps require slurry particle removal after CMP. Post-CMP cleaning used a dilute SC-1 solution in a prototype full-immersion cleaning tank equipped with a megasonic line source transducer for radially diverging acoustic agitation. This approach replaces the typical brush cleaning step with a noncontact process.
Dilute SC-1/megasonic cleaning reduces the surface particle concentration enough to allow AFM analysis even though the slurry was allowed to dry on the wafer surfaces for more than a week during transport. Slurry particles (d = 30 nm) were completely removed from a significant number of AFM measurement sites.
AFM of planarized oxides
The oxide surface morphology after CMP is characterized by AFM [12] frequency plots of surface elevations (512 lines/scan, 512 points/line, 20 ? 20-?m scan area), obtained at five equally spaced sites along a radius. The resulting histograms measure surface roughness and can also be used to estimate surface hardness of the different compositions by comparing the maximum surface relief (MSR) of each film. MSR can be defined as the total depth range of the histogram, after removing large particle features (Fig. 8). Intuitively, the MSR measures the local maximum "scratch depth" resulting from slurry particle indentation during polishing, superposed onto the low spatial frequency variations occurring within the scan area (fmin = 100 mm-1). MSRs for different oxides are a qualitative measure of their relative hardness and should be proportional to the average removal rate [13].
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Figure 8. Histograms of surface morphology of CMP`d oxides indicates the relative hardness by comparing the maximum surface relief (MSR) of different oxides. The MSR is defined here as the deepest "scratch" observed after large particle features are removed (4.48 nm).
Under the polishing conditions used, a layer thickness comparable to the observed MSR (<10 nm) is removed every few seconds. Since the carrier unloading transient is a significant fraction of this time, we expect the surface roughness histogram obtained by AFM to differ from the distribution established at equilibrium during CMP. Consequently, we have refrained from analyzing the shapes of the distributions. If the unloading transient is comparable from run to run, however, the MSR should still provide relative hardness data.
The MSRs of all the APCVD films are similar, suggesting that the hardness of the layer undergoing CMP is comparable for all APCVD films, whether doped or not (Table 4). Preliminary tests using the AFM as a nanoindenter provided similar results; all APCVD films showed similar surface hardness.
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Although the average MSR observed for the thermal oxide is much smaller than for the densified, undoped APCVD films, their removal rates are similar. Only minor density differences are expected between the two oxide classes, but the stress and silanol content are expected to be different (0.5wt % for APCVD films, essentially dry for thermal oxide). The silanol content in undoped APCVD films apparently decreases the surface microhardness without significantly affecting the macroscopic CMP removal rate.
The ratio of normalized hardness (measured in terms of relative Si-O bond density) to modulus of elasticity (H/E) was previously reported to be linearly proportional to the normalized removal rate for undoped oxides [13]. Cook proposes that the oxide CMP process is dominated by surface mechanics and insignificantly affected by hydration kinetics [14]. Our AFM and removal rate data, however, indicate that the CMP rate varies significantly with B/P doping while the H/E ratio remains unchanged (assuming a slow dependence of modulus on doping). Both hydration kinetics and surface mechanics appear to be important. We suspect that silanols, a near surface network modifier, can dominate macroscopic reproducibility of doped oxide CMP performance.
Conclusion
As expected, existing PMD process techniques for 200-mm wafers appear to be wholly extendible to the 300-mm generation. Tool development is beyond the demonstration stage and is ready for process integration development. Additional features of the RTP behavior of APCVD BPSG have been demonstrated and the results of the oxide CMP removal rate uniformity emphasize the critical role of uniform slurry distribution for polish uniformity. Slurry removal by noncontact methods has been demonstrated for 300-mm wafers. AFM studies of oxide CMP mechanisms indicate that a measure of the near surface hardness can be obtained from histograms of surface roughness.
The participating organizations in this PMD demonstration added to their 300-mm experience base and the experiment increased the awareness of other 300-mm capabilities in the equipment industry. As a method of establishing process standards and market information, though, it appears that the major success was in perpetuating existing rumors. Clearly, national centers are needed for complete 300-mm process development, but informal collaborations can contribute to short loop process development.
Acknowledgments
Many individuals at the participating organizations contributed significantly to this work. We gratefully acknowledge the assistance and cooperation of our co-workers, especially J. McGahan (Nanometrics); K. Goyal, J. Westphal and M. Mogaard (WJ); R. Goodall (I300I); D. Levedakis, C. Barns and K. Holland (IPEC); M. Serry (DI): and J. Agnello (Verteq).
References
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13. C.W. Liu, B.T. Dai, C.F. Yeh, "Characterization of the Chemical-Mechanical Polishing Process Based on Nanoindentation Measurements of Dielectric Films," J. Electrochem. Soc. 142, p. 3098, 1995.
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WILLIAM SCHAFFER is the senior technologist for Watkins-Johnson SEG Division. He contributes to the development of deposited dielectric technology for sub-0.25-?m IC processing. Watkins-Johnson, 2525 N. First St., San Jose, CA 95131; ph 408/953-5684; email [email protected].
DENNY SCHEY serves as product manager for advanced metal CMP at IPEC Planar.
MIKE BOWMAN is the CMP technology program manager for I300I, where he is responsible for CMP equipment and integration processes for the transition to 300-mm wafer sizes.
WILLIAM MCGAHAN is the advanced metrology and engineering manager for Nanometrics. He develops reflectance and spectroscopic ellipsometry techniques for semiconductor process control.
JEFFERY BOISEN is in the technical marketing group at Moore Technologies.
YALE STRAUSSER is the application specialist at Digital Instruments and develops new applications for atomic force and scanning capacitance microscopes for semiconductor processing.
MARIO BRAN is the director of technology research for Verteq Process Systems and develops advanced noncontact cleaning techniques for semiconductor applications.