Canon introduces SOI-EPI wafer
09/01/1997
Canon introduces SOI-EPI wafer
Silicon-on-insulator (SOI) wafers, which offer improved isolation and reduced capacitance relative to bulk silicon, are promising for high-speed and low-power devices, especially in telecommunications. Market acceptance has so far been hindered by cost, and by the relatively poor quality of the silicon layer.
Canon Inc. has developed a new "epitaxial layer transfer" (ELTRAN) method for SOI wafers. The bond and etch-back method produces an epitaxial silicon device layer. According to Takao Yonehara, ELTRAN project manager, in a presentation at SEMICON/West, the key manufacturing step is Si epitaxial growth on a porous silicon sacrificial layer (see Fig. 1).
The porous silicon layer is created by anodizing boron-doped wafers in 49% HF + C2H5OH, creating a 10-20-micron thick layer. Baking in a hydrogen ambient fills the pores and minimizes surface energy, "sealing" the surface and creating a smooth substrate for epitaxial silicon deposition. After conventional CVD of epitaxial silicon, a thermal oxide layer protects the silicon surface from impurities at the bonding interface.
The device wafer is then bonded, epilayer down, to a "handle wafer," and mechanical grinding removes the device wafer. The porous silicon layer is thick enough to ensure that the grinding step terminates inside it, leaving the epitaxial layer intact (see Fig. 2).
Finally, a selective etch with HF/H2O2 removes the porous silicon layer (see Fig. 3). As the etchant penetrates the pores, the pore walls etch, finally collapsing. This collapse ensures that the porous silicon layer is completely etched without damage to the epitaxial layer.
Yonehara points out that bonding SOI methods are generally expensive, because two wafers are consumed for each device wafer. With the ELTRAN process, the device wafer need not be prime quality silicon, since the epitaxial deposition controls the properties of the active layer. Likewise, the bonding, or "handle" wafer could be transparent glass, rather than silicon. Furthermore, recent work suggests that the bonded pair can be mechanically split at the porous silicon layer, allowing recycling of the device wafer. - K.D.
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Figure 1. ELTRAN wafer fabrication process.
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Figure 2. XTEM image of the ELTRAN structure, before porous silicon removal. Note the smooth interfaces on both sides of the epitaxial silicon layer.
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Figure 3. Etching mechanism of porous Si on nonporous epitaxial Si by HF/H2O2.