Shallow trench isolation for sub 0.25-um IC techniques
09/01/1997
Shallow trench isolation for sub-0.25-?m IC technologies
Somnath Nag, Amitava Chatterjee, Semiconductor Process and Device Center, Texas Instruments Inc., Dallas, Texas
Transistors in ICs have conventionally been isolated by growing thick SiO2 thermally in the regions between them. This so-called local oxidation of silicon (LOCOS) masks off the active areas with a layer of silicon nitride (Fig. 1a). The main drawback of LOCOS, the unacceptably large dimension of the "bird`s beak," limits its utility for the smaller geometries in sub-0.25-?m designs. Shallow trench isolation (STI), in contrast, uses deposited dielectrics to fill trenches etched in the silicon between the active areas. In principle, it is only limited by the lithography, etch, and gap-fill depositions, which have thus far scaled with transistor technology. Therefore, STI is an attractive alternative to LOCOS for deep submicron ICs. This article discusses key considerations in the development of the STI module and highlights potential problems for large-scale implementation of STI in wafer fabrication.
Low topography, which helps meet planarity requirements and tight lithography budgets; and improved minimum isolation space, latchup, and junction capacitance are added advantages of STI. Depending on the process scheme, STI can be implemented at temperatures significantly lower than required for thermal oxide growth in LOCOS, eliminating any possible stress and warpage problems induced by high-temperature processing. Lower-temperature processes can also potentially increase throughput and reduce wafer cost. STI has recently been introduced into 0.35-?m manufacturing and is still being optimized for volume production.
Integration of shallow trench isolation
The STI process (Fig. 1b) starts out with a 100-150 ? thermal oxide grown on a bare Si wafer, followed by a 1500-2000 ? thick furnace nitride layer. Etching through the nitride, oxide, and silicon forms trenches about 0.5-?m deep; then a 150-200 ? thick, thermal oxide liner, grown along the etched trench sidewalls, rounds the corners at the top and bottom of the trench. Next, 9000-11,000 ? of oxide is deposited in the trenches and then planarized by chemical-mechanical planarization (CMP). Post-CMP cleanings use hydrofluoric acid (HF) deglazes. As discussed below, optimal oxide properties may require a high-temperature anneal step immediately after oxide deposition. Then hot phosphoric acid strips off the nitride, a CMP stop layer, followed by implants for field threshold voltage (Vt) adjust or channel stop. The thermal pad oxide is also etched off with HF. The deposited oxide in the trenches, exposed during all the HF deglazes, suffers some etch loss. After pad oxide removal, the gate oxide is regrown and conventional transistor flow continues.
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Figure 1. a) Process flow for conventional LOCOS isolation; b) process flow for STI scheme.
Polysilicon gates deposited over the active areas also extend over the oxide in the trenches. As in LOCOS, the polysilicon in the field areas should have thicker oxide underneath it, so the field Vt is significantly higher than that of the device. In STI, however, excessive oxide loss over the trenches during the HF deglazes could cause the oxide surface there to be at a lower level than the active silicon, exposing the trench corner. The polysilicon would then wrap around the upper corner of the trench, dipping as it went from the active area to the trench (Fig. 2). This polysilicon, together with the thermal oxide at the corner of the trench, which is also thinned by the post-CMP HF etch, constitutes a parasitic edge transistor with a lower Vt than the active device. A sub-Vt "hump" in the I-V characteristic results. This parasitic transistor is one of the main problems to be addressed in STI fabrication. The trench etch, liner oxidation, trench-fill oxide deposition, and planarization processes must be optimized to prevent polysilicon wraparound. Other issues specific to each step are addressed in the following sections.
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Figure 2. The "gate polysilicon wraparound" problem at the trench corner.
Role of the silicon nitride layer
The silicon nitride layer is primarily a CMP stop layer over the active silicon areas. CMP has an across-wafer variation as well as an inherent pattern dependence. The polish rate over isolated narrow geometries is much higher than that over wide or dense array structures. The silicon nitride layer, therefore, has to be thick enough to leave a reasonable amount of nitride even in areas that suffer overpolish.
The minimum nitride thickness must also consider coverage of the trench corner by the fill oxide after nitride strip. When the CMP polish rate of the trench-fill oxide is reasonably comparable to that of the nitride, the post-CMP surface of the nitride is approximately level with the surface of the trench-fill oxide (Fig. 1b). Since some of the trench oxide is etched off during the post-CMP cleanups, the nitride thickness will determine the step-height between the active area silicon and the surface of the trench-fill oxide, which should be large enough to avoid the parasitic corner transistor effect. Optimizing the nitride thickness within these limits allows accurate pattern transfer without undesirable interference effects [1].
The importance of trench profile and surface
The entire stack - nitride, pad oxide, and silicon - is etched to form trenches whose depth can vary from 0.35-0.5 ?m, depending upon device design. Trench sidewall slopes of about 75-80? avoid a sharp corner in the active silicon at the top of the trench. Such a sharp profile would create a high field region and could result in leaky devices or GOI (gate oxide integrity) problems. Sloped walls and rounded corners also allow void-free and seamless gap-fill during the trench-fill oxide process. A thermal oxide liner, grown on the trench sidewalls, passivates the etched silicon surface and creates a barrier between the silicon and the deposited trench-fill oxide. The final radius of curvature of the upper (and lower) corner of the trench depends on the thickness of the pad oxide and the thickness of the trench liner oxide. The oxidation process conditions can also be used to control the radius of curvature of this corner [2].
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Figure 3. a) Seam and sinkhole formation with the O3-TEOS trench-fill process; b) inadequate gap-fill with the LPCVD TEOS process.
The critical trench-fill process
The trench-fill process is the key to isolation performance. A number of options are in various stages of development. Deposited oxide processes, traditionally used at or above the premetal dielectric level, now have to meet more stringent specs for STI at the transistor level. Both process and film properties can affect the electrical performance of the STI module.
The deposition process window must be chosen to prevent changes to trench profile, physical damage, or electrical damage to the trench surface. Electrical damage to trench sidewalls can create current leakage paths between the transistor source and drain as well as between isolated active areas. Physical damage to the trench would reduce transistor width and cause undesirable electrical behavior.
The dielectric used to gap-fill the trenches must be mechanically and electrically robust to withstand multiple HF deglazes for post-CMP cleanup and pad oxide strip, during which trench oxide loss should be negligible. The trench-fill oxide will also be exposed to temperatures above 800?C during the source/drain anneals and the borophosphosilicate glass reflow cycles. Therefore, it should be thermally stable at these high temperatures and should have low shrinkage during thermal cycling. Otherwise the level of oxide in the trench would drop below that of the active silicon and cause poly-wraparound. For the same reason, the CMP polish rate of the trench oxide should be low and comparable to silicon nitride. Contamination levels of mobile-ions and metallics in the oxide must be below 5 ? 109/cm2, as required for gate oxides.
The trenches should be filled without voids or seams in the oxide. Voids that extend above the level of active silicon could be opened up during CMP and could be filled with polysilicon during the gate deposition. Similarly, seams are weak areas on the oxide surface and are liable to etch off preferentially during a HF deglaze.
While some of these oxides require a high-temperature anneal in order to stabilize the material and reduce etch rates, an oxide that does not need such an anneal offers lower wafer warpage and stress, and reduced cycle time and cost of ownership. Oxide processes considered thus far fall into three categories.
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Figure 4. Bottom-up, seamless, void-free gap-fill of trenches using HDP-CVD.
TEOS processes. Oxides deposited using the O3-TEOS chemistry generally tend to have seams at the center of the trench due to the conformal nature of the gap-fill. For instance, subatmospheric (SA) and atmospheric pressure (AP) CVD oxides can have sinkholes along this weak seam after HF exposure (Fig. 3a). However, gap-filling of these oxides is complete even for sub-0.2-?m trenches. O3-TEOS oxides require a high-temperature anneal to reduce HF etch rates and may also need seed/cap layers. Low-pressure (LP) TEOS, which uses the TEOS/O2 chemistry, leaves voids for sub-0.5-?m-wide trenches (Fig. 3b).
Spin-on-glasses. The extremely good gap-filling capability of inorganic spin-on glasses (SOGs) such as hydrogen silsesquioxane (HSQ) would make them attractive for the STI application. However, the 25-30% shrinkage of these materials at high temperatures during transistor fabrication causes delamination of the oxide from the trench sidewalls. SOGs also need a post-deposition anneal at 850?C to reduce their HF etch rate.
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Figure 5. Damage to trench corners by excessive sputtering during HDP-CVD.
HDP-CVD oxide. Simultaneous ion sputtering during the 350?C high-density plasma (HDP)-CVD deposition process densifies the film and results in a high-quality oxide. Sputtering also prevents oxide "breadloafing" at the upper corners of the trench; the depositing oxide can fill from the bottom of the gap without pinch-off [3]. HDP-CVD gap-fill is seamless due to the bottom-up filling and is void-free for gaps down to 0.16 ?m (Fig. 4). Excessive sputtering can damage the trench corners (Fig. 5), however, and allow poly-wraparound and transistor width reduction. Moreover, sputtering damage to the gate oxide and the liner oxide can cause transistor leakage and low GOI. While the sputtering component is required for gap-filling of narrow trenches, it can also cause physical and electrical damage to the transistors.
Process-sequencing solutions, such as initiating the deposition with a low sputter component and then increasing the sputter component for gap-filling once a protective seed layer is deposited on the trench surface, can avoid sputter damage. However, the oxide quality in liners without ion bombardment is poor. Post-CMP HF dips etch away this weak liner oxide, forming a groove at the top of the trench that then fills with polysilicon during gate deposition. The gate etch is unable to remove the polysilicon from these grooves, and therefore conductive filaments form that can cause leakage paths between transistor terminals. For STI, the HDP-CVD process must run in a regime where void-free gap-fill is achieved without causing sputter damage. Electrical measurements on perimeter-intensive structures indicate that the sputter damage is an edge phenomenon.
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Figure 6. Across-wafer variation of step at trench edge for various gap-fill processes. Negative values indicate that the level of the trench surface is lower than the level of the active area.
Planarization of the deposited trench-fill oxide
As discussed above, the deposited oxide has to be polished so that the nitride over the active areas is exposed and level with the surface of the oxide in the trench. Typically, isolated narrow structures polish quicker while close-spaced dense arrays and wide blocks have slower CMP rates. CMP may also have an across-wafer nonuniformity. Overpolish beyond nitride exposure not only reduces nitride thickness but also forces the CMP pad to polish two different materials simultaneously, nitride over active area and oxide over trench. If, for instance, the CMP rate of the trench oxide is much higher than that of the nitride, then significant "dishing" of the trench oxide and erosion of the trench corner can result.
Figure 6 shows the across-wafer uniformity of CMP for the different trench-fill materials, measured on the same narrow transistor in each die. HSQ-SOG shows negative values - the trench surface is lower than the active area - for this step height for all die across the wafer. The center-to-edge variation seen for SACVD oxide results from interaction between the deposition profile and the CMP characteristic. The die at the edge of the wafer would have sub-threshold leakage currents, while the ones at the center would not. Densified TEOS and as-deposited HDP-CVD oxides show positive step-height values, although there is a marginal step-height variation across the wafer.
Similar step-height measurements at the edge of the trench indicate that more oxide remains in the trench for wider structures than for narrower structures. This problem, explained by the higher polish rates for narrow and for isolated structures, can be overcome by using dummy active areas [4] around isolated structures. The dummy regions create a higher pattern-density and reduce CMP rates. A 500-? layer of nitride deposited on top of the trench-fill oxide prior to CMP can also prevent overpolish in isolated narrow regions [5] (Fig. 7).
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Figure 7. Equalization of CMP rates for narrow and wide trench structures by the use of a nitride overlayer.
Summary
The trench-fill process, the fill dielectric, and its interaction with etch, thermal oxidation, and CMP processes, all have a significant impact on STI integration. Polysilicon wraparound at the trench edge, which is directly responsible for poor transistor characteristics, results from such interaction between the various process steps. Optimization of the unit processes involved in STI allows its easy integration into submicron CMOS flow.
Acknowledgment
The authors thank G. Hames, K. Joyner, P. Kwok, M. Mason, D. Mercer, P. Nicollian, D. Rogers, and I-C. Chen for technical contributions and discussions.
References
1. Private communication.
2. P. Pan et al., "Trench Corner Rounding by Using Rapid Thermal Oxidation in NF3/O2/Ar Ambient," Proc. ECS Fall Meeting, p. 748, 1994.
3. S. Nag et al., "Comparative Evaluation of Gap-fill Dielectrics in Shallow Trench Isolation for Sub-0.25-?m Technologies," IEDM Tech. Digest, pp. 841-844, 1996.
4. I. Ali et al., CMP-MIC Conf., pp. 249-255, February 1996.
5. J. Boyd et al., "A One-step Shallow Trench Global Planarization Process Using Chemical Mechanical Polishing," ECS Proc., Vol. 95-5, p. 290, 1995.
SOMNATH NAG received his PhD degree from Pennsylvania State University in 1992. He is a member of the technical staff at Texas Instruments` Semiconductor Process and Device Center (SPDC), where he has worked on thin-film technology development since 1994. Prior to this, he was a process development engineer and productization team member responsible for transferring technology from R&D to manufacturing at TI`s Houston wafer fab. Texas Instruments Inc. (TI), SPDC, 13570 N. Central Expressway, MS 3701, Dallas, TX 75243; ph 972/995-9649, fax 972/995-1916.
AMITAVA CHATTERJEE received his PhD degree in electrical engineering from RPI. He joined Texas Instruments in 1985, where he is a senior member of the technical staff at TI`s SPDC. Chatterjee has worked in the areas of CMOS latchup, ESD, MOS circuit models, DRAM, low-power CMOS, and isolation. He is currently involved with scaling to sub-0.1-?m transistors.