Brush scrubbing emerges as future wafer-cleaning technology
07/01/1997
Brush scrubbing emerges as future wafer-cleaning technology
Diane Hymes, Igor Malik, Jackie Zhang, Ramin Emami, OnTrak Systems, San Jose, California
Much of the early brush-scrubbing data, with a few exceptions [1], was not published. Therefore, many experienced people in the wafer-cleaning field are still under the misconception that PVA brush scrubbing is not effective for the removal of submicron surface particles. The data presented in this article demonstrates the ability of double-sided scrubbing to remove particles as small as 0.12 ?m without damaging the wafer surface.
PVA brush scrubbing today
The widespread acceptance of chemical mechanical planarization (CMP) has propelled brush scrubbing into the mainstream of semiconductor wafer cleaning. Brush scrubbing is considered the most effective method for removing slurry used in the CMP polishing process [2-5]. Double-sided scrubbing (DSS) is an interaction of the wafer surface, PVA brush, and particles in an aqueous environment. The surfaces of interest include the surfaces of particles (contamination), the brush, and the wafer. The cleaning action consists of the mechanical dislodgment of particles from the wafer surface by the brush. After that, the particles stay suspended in the liquid layer above the surface of the wafer and go over the edge of the wafer to the drain as the liquid is continuously delivered to the wafer surface. Such a scenario assumes that once a particle is dislodged, it never reattaches to any surface and quickly moves away within the liquid layer. Two possible events must be prevented once the particle is dislodged:
1) reattachment of the particle to the wafer surface, and
2) attachment of the particle into the porous brush structure (brush loading).
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Figure 1. Dependence of the zeta potential (ZP) on pH.
The best way to prevent particle reattachment and brush loading is to control the electrostatic interactions, in particular the zeta potential (ZP). ZP is useful for understanding the behavior of surfaces immersed in liquids. It may be thought of as an "effective" surface potential that is different from the surface potential because of the presence of a stagnant liquid layer (Stern layer) near the surface. ZP is the value of the electric potential on the boundary between the Stern layer and the diffuse layer (the layer that is mobile but whose electric potential is still affected by the surface potential). The extent of the diffuse layer is defined by the drop of the potential to zero, where it is in equilibrium with the surrounding liquid. The ZP and surface potential always have the same sign, with ZP having the smaller absolute value. Keeping the ZPs of all the surfaces of interest at the same polarity and maximum absolute value maximizes the mutual repulsions necessary for effective cleaning. The best way to accomplish this is with alkaline (basic) pH values [6-9].
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Figure 2. Schematic of the DSS-200 double-sided scrubber from OnTrak Systems.
At pH values above 9, all surfaces usually encountered in wafer cleaning have negative ZPs, satisfying the requirement for mutual repulsions during the cleaning process (Fig. 1). The most popular post-CMP brush scrubbing process uses a room temperature solution of dilute ammonium hydroxide, in a concentration range of 0.15-1.6% [3-6]. This high-pH process solution permits the brushes to remain clean, even with exposure to tens of thousands of slurry-laden wafers. This environmentally friendly process is used in mass production in fabs worldwide.
System configuration
The OnTrak DSS-200 (Fig. 2) wafer cleaning system was used in this study. The wafer moves from left to right through four
sequential stations: the input station, the two brush-cleaning stations, the spin rinse/dry station, and the unload station. The input station sprays water on the incoming wafer to keep it wet prior to scrubbing. The wafer is then transferred to the first of two identical brush stations where both its front and back surfaces come in contact with the PVA brushes. The wafer rotates in the horizontal plane while the two PVA brushes rotate around a horizontal axis (Fig. 3). Deionized water (DIW) flows continuously through the core of all the PVA brushes. The diluted ammonium hydroxide is applied during the brush cleaning. Following brush cleaning, the wafer is transferred to the spin rinse/dry station where DIW sprays onto the front and back prior to application of heat during the drying cycle. An edge-handling unloader transfers the dry wafer to the output station.
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Figure 3. Detailed view of the wafer-cleaning setup inside the DSS-200 brush box.
Brush scrubbing can be applied to both CMP and non-CMP cleaning applications in both the front and back ends of the semiconductor manufacturing process. Brush scrubbing is commonly used subsequent to laser-marking of silicon nitride films, after deposition of oxide and metal films, and after tungsten-etchback in the interconnect sequence. Brush scrubbing is also used to clean monitor wafers for a variety of process systems, including CVD/PVD systems and wet benches. This approach to cleaning, called general fab cleaning, is very common in Japan, Korea, and Taiwan, and is gaining popularity in Europe and the US [8-11].
Experimental
Experiment #1 - post-polish silicon cleaning. To simulate the cleaning challenge of the post-polish silicon surface, 200-mm silicon wafers were dipped in a colloidal silica slurry used for silicon wafer polishing (Nalco 2350 used in 20:1 dilution with DIW). A wafer inspection system (e.g., Tencor Surfscan 6420) measured the wafers before exposing them to the slurry and then again after slurry dip and subsequent brush cleaning. The particle measurements were made at =0.12 ?m, =0.16 ?m, =0.2 ?m, and =0.3 ?m with 3-mm edge exclusion.
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Figure 4. Tencor 6420 defect maps (=0.12 ?m) of prime 200-mm Si wafers, a) before and b) after a slurry dip in Nalco 2350 Si polishing slurry followed by DSS-200 clean. Note that all of the slurry has been removed by the cleaning.
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The slurry contributes tens of thousands of particles to the wafer surfaces. The goal is to remove the particles to obtain a final defect count which is comparable to that of the starting wafer surface. Table 1 indicates that the brush scrubber removed the silica particles at all of the sizes measured. The table provides the average defect concentration on the incoming wafers and the average defect concentration on the wafers after the slurry dip and brush clean, as measured by Tencor 6420, with 3-mm edge exclusion. Figure 4 shows wafer maps obtained before and after slurry dip and subsequent brush scrubbing.
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Figure 5. Removal of defects of =0.12 ?m from intentionally contaminated, 200-mm epitaxial Si wafers.
Surface roughness was measured by atomic force microscopy (AFM). The as-received silicon surface is characterized by a root-mean-square roughness of RRMS = 0.14-0.15 nm over a scan area of 2 ? 2 ?m. The RRMS of the post-cleaned surface over the same scan area is 0.13-0.14 nm. No difference in surface microroughness was observed after slurry dip and brush cleaning. No damage or surface roughening resulted from the brush cleaning.
Experiment #2 - cleaning of epitaxial silicon wafers. The second experiment demonstrates the ability of brush scrubbing to remove submicron particles from 200-mm epitaxial silicon wafers. The wafers used in this experiment had high levels of particles from a prolonged storage period. Figure 5 shows the pre-clean and post-clean particle data gathered at =0.122 ?m with an edge exclusion of 6 mm. Again, the brush scrubbing system demonstrates the ability to remove particles as small as 0.122 ?m.
The defect level displayed in Fig. 5 (average of 185 at =0.122 ?m) does not represent the lowest achievable level by this cleaning method. The lowest defect level obtainable from high-quality silicon wafers is primarily determined by the quality of the DIW. For example, the final particle average of ten 150-mm epitaxial silicon wafers was 5.8 for defects with sizes =0.12 ?m (Fig. 6) after a DIW system upgrade. The upgraded DIW reduced dissolved silica from approximately 20 to <5 ppb and total oxidizable carbon (TOC) from approximately 40 to <10 ppb.
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Figure 6. Final defect level at =0.12 ?m after brush cleaning of 150-mm epitaxial silicon wafers using ultra pure DIW.
Experiment #3 - post W-CMP cleaning. Dilute HF may be used in the scrubber following W-CMP (chemical mechanical planarization to define the W plugs). HF is highly desirable for removing trace metals from the surface through the etching of a thin layer of SiO2 (< 50 ?). However, since the surface also has areas of W plugs surrounded by an adhesion layer (most often Ti), damage to these materials must be avoided.
We used AFM to study the effects of brush cleaning for removal of submicron particles on the surface of a tungsten plug that had been contaminated with polishing slurry, in a back-end-of-line (BEOL) cleaning application. Figure 7 shows the atomic force images of a 2.0-mm dia. tungsten plug with residual slurry contamination and then the same plug with the complete removal of slurry contamination by the dilute HF brush clean. The cleaning process uses dilute ammonia in the first brush station and dilute HF in the second brush station. The HF is dilute enough that no attack to the adhesion layer or barrier layer occurs. The brush clean removes slurry particles that are approximately 0.1 ?m, without causing any mechanical or chemical damage to the plug structure. There is no evidence in the high-resolution scan of any morphological changes to the Ti and TiN layers that surround the W plug.
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Figure 7. AFM images of the same W plug before and after cleaning with dilute HF in the DSS-200; the slurry contamination from the CMP process was completely removed by the dilute HF scrubbing process without damaging the liner materials.
Experiment #4 - cleaning the liner layers Ti and TiN. The last example demonstrating the effectiveness of double-sided scrubbing comes from the BEOL as well. Many of the overall yield and reliability issues in semiconductor manufacturing result from the interconnect manufacturing sequence. For example, particle contamination originating in the equipment used for the deposition of Ti and TiN can result in killer defects in the completed device (e.g., electrical shorts, metal peeling). Cleaning the Ti and/or TiN layers before depositing the conductor material can add robustness to the manufacturing process.
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Table 2 shows the results obtained using dilute ammonia in both brush stations to clean as-deposited Ti and TiN films on 150-mm wafers. The total defect level was significantly reduced for defects =0.16 ?m. The reduced standard deviation (Table 2) corresponds to an overall lower and tighter defect distribution with the use of brush cleaning.
Summary
Process performance. One clear trend in multilevel interconnect technology illustrated in The National Technology Roadmap for Semiconductors [11] is the increase in the number of levels of metal interconnect. In the next few years, we expect three metal levels for DRAM technology and four-to-six levels for state-of-the-art microprocessor technology (Table 3). This significant increase in interconnect density places great importance on the interconnect yield in the total functional yield, evidenced by the drastically decreasing critical defect size and defect concentration requirements.
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Brush scrubbing, with the use of only dilute and friendly chemistries, is a proven technology for the removal of =0.12 ?m particles. Most current technology for particle removal becomes far less effective as the critical defect size approaches 0.1 ?m. In the backend, compatibility with the interconnect metals limits the types of chemistries that may be used. Consequently, brush scrubbing is expected to play a more prominent role in future cutting-edge cleaning applications such as silicon wafer cleaning and cleaning in the front and back ends of the semiconductor manufacturing process.
Future requirements - flexibility of process, scaleability to 300 mm, safety, and environmental. Process flexibility is important for future cleaning technology. The next-generation brush scrubber will have greater chemical and mechanical capabilities, allowing the technology to evolve from simple scrubbing to an even more versatile, chemical-mechanical cleaning method. New cleaning processes will extend chemical-mechanical cleaning to many new and challenging cleaning applications that, to date, have only been approached by more complicated wet-bench cleaning sequences. The brush scrubber`s ability to clean with extremely dilute solutions of room temperature, nontoxic chemicals and/or DIWis well suited to the stringent environmental and safety requirements of today and the even more stringent requirements of next-generation manufacturing technology.
Today`s brush-scrubbing systems are cassette-to-cassette, single-wafer processing systems that are easily sized to the wafer size. This system configuration lends itself well to 300-mm wafer processing, which is expected to be largely single-wafer processing. For these four reasons-process performance (especially submicron particle removal), process flexibility, scaleability to 300 mm, and an environmentally friendly process chemistry-brush scrubbing is considered a highly viable and desirable cleaning option for next-generation technology.n
Acknowledgments
We would like to thank Willy Krusell and John de Larios of OnTrak Systems for numerous discussions and review of this article.
References
1. C. Krusell, D. I. Golland, "Cleaning Technologies for High Volume Production of Silicon Wafers," Semiconductor Cleaning Technology, Meeting of the Electrochemical Society, Florida, 1989.
2. W.C. Krusell, J.M. de Larios, J. Zhang, "Mechanical Brush Scrubbing for Post- CMP Clean," Solid State Technology, p. 109, July 1995.
3. J.M. de Larios, W.C. Krusell, "The Challenges of Post-Metal Polish Clean," SEMICON Southwest, Austin, October 1995.
4. S.R. Roy, et al., "Postchemical-Mechanical Planarization Cleanup Process for Interlayer Dielectric Films," J. Electrochem. Soc., Vol. 142, No.1, January 1995.
5. J.M. de Larios, M. Ravkin, D. Hetherington, J. Doyle, "Post-CMP Cleaning for Oxide and Tungsten Applications," Semiconductor International, May 1996.
6. A number of Physical Chemistry and Electrochemistry textbooks, e.g., A.W. Adamson, Physical Chemistry of Surfaces, Fifth Edition, Wiley, 1990.
7. D. E. Jan, S. Raghavan, "Electrokinetic Characteristics of Nitride Wafers in Aqueous Solutions and their Impact on Particulate Deposition," J. Electrochem. Soc. 141, 2465, 1994.
8. W.C. Krusell, I.J. Malik, F. Mohr, D.J. Hymes, "Double-Side Scrubbing Beyond Post-CMP Cleaning," Fourth International Symposium on Cleaning Technology in Semiconductor Device Manufacturing, Fall 1995 Electrochemical Society Meeting, p. 409.
9. J. Zhang, I. Malik, M. Ravkin et al., "Double Sided Scrubbing: An Effective Method for Multiple Cleaning Applications," SEMICON China 95, September 19, 1995.
10. D.J. Hymes, I.J. Malik, "Effective Surface Cleaning with Double-Sided Scrubbing," Micro., p. 55, October 1996
11. The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1994.
DIANE HYMES received her MS and PhD degrees in materials science and engineering from Brown University, Providence, RI, in 1984 and 1987, respectively. She is director of cleaning process technology at OnTrak Systems. OnTrak Systems Inc., 1010 Rincon Circle, San Jose, CA 95131; ph 408/577-1010, fax 408/952-5441.
IGOR MALIK received his MS degree in chemical engineering in 1984 from the Institute of Chemical Technology in Prague, Czech Republic, and his PhD degree in physical analytical chemistry in 1989 from the University of Illinois at Chicago. He works at Chartered Semiconductor in Singapore.
JACKIE ZHANG received her BS degree in mechanical engineering from the Northeast University in Liaoning, China, and her MS degree in mechanical engineering from San Jose State University. She is a product engineer at OnTrak Systems.
RAMIN EMAMI received his B. Tech. Degree in marine engineering from DMET College in Calcutta, India, and is currently pursuing graduate studies in physics. He is a process development engineer at OnTrak Systems.