Large tilt-angle implantation enables smart-power Ics
07/01/1997
Large tilt-angle implantation enables smart-power ICs
The latest generation of Thompson-CSF`s BCD (bipolar, CMOS, DMOS) process, BCD5, can combine numerous CMOS device types along with high-voltage DMOS power transistors on a single substrate. BCD5 uses 0.6-?m linewidths to implement microprocessor cores and EPROM, EEPROM, or flash EPROM memory. The DMOS transistors operate at 16, 20, 40, or 80 V (see figure).
Such devices can be used in the automotive field to make very dense engine-control units as well as sophisticated smart sensors and single chip smart switches for multiplex wiring circuitry. In computers, they can be employed to integrate hard disk drives or to realize complex, powerful audio amplifiers.
The company achieves compatibility between nonvolatile memories and LDMOS by replacing conventional DMOS manufacturing processes, consisting of high-temperature diffusion steps, with an innovative approach that exploits a "large angle of tilt" implantation technique.
Conventional manufacturing processes use long, high-temperature drive-in steps in order to obtain p-body lateral diffusion regions deep enough to avoid source-drain punch-through and achieve a peak concentration compatible with a low threshold voltage (typically 1.5-2.5 V). But high-temperature, long duration steps aren`t suitable for achieving the desired reduction in feature sizes and would dramatically increase the defects in thinner oxide layers. This is particularly true for nonvolatile memory devices, where oxide thicknesses <80 ? are typical.
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BCD5 can achieve a range of device types on a single substrate.
Several techniques exist to overcome this incompatibility. One uses p-well diffusion for the LDMOS body region. But, with this method, the device loses the self-aligned channel characteristic, resulting in a less dense packing capability.
Another possible solution is to add a dedicated gate oxide and polysilicon level before CMOS formation. A p-body high-temperature drive-in step can then be introduced without perturbing the CMOS block. This approach is modular, but it adds masks and process complexity, and is less suitable to further DMOS gate-oxide scaling.
In the BCD5 process, the DMOS body is realized by means of a large tilt-angle implantation masked by the already defined polycide gate (polysilicon/WSi2), without introducing any dedicated thermal treatment. According to simulation results, a 45? angle is the best compromise between lateral and vertical junction depth. Larger tilt angles are more effective in pushing charge in the DMOS active channel; nevertheless, two drawbacks are evident:
Shadow effect from the polycide gate and photoresist stack may limit the source window width, affecting the cell pitch.
DMOS ruggedness is reduced because the charge in the intrinsic parasitic NPN base decreases.
Lower tilt angles reduce channel charge and length, causing premature punch through; moreover, statistical process control worsens because the implanted charge is more affected by the thickness spread of the stopping layers` stack.
The strong stopping power of the refractory metal employed as gate strips, and its appropriate thickness, allow implanting the p-body layer at a moderately high energy. Simulations showed that energies up to 150 KeV are suitable.
For different oxide thicknesses vs. p-body implant dose, with a 200 ? thick gate oxide, Vth voltages between 1.0 and 1.3 V are measured. This is quite low for a self-aligned channel, allowing the DMOS transistors to be driven directly by the on-chip 5-V CMOS circuitry, without a significant loss in Ron.
When high operating voltages are required for the DMOS transistors, dedicated low doping n wells are added to the baseline flow. In this way, breakdown voltages up to 60 V are achieved using a field-oxide self-aligned drain structure. To further increase BVdss, the heavily doped N+ buried layer is replaced with a low-doping buried well.
The CMOS circuitry is implanted on an n epilayer grown on a p-type substrate after formation of multiple n-type and p-type self-aligned buried layers. The junction isolation structure is obtained by the conjunction of the upward diffusing p buried layer with the downward diffusing p well. - Charles H. Small, senior editor Computer Design