CMP takes on STI
07/01/1997
CMP takes on STI
As oxide CMP matures, development efforts are focusing on shallow trench isolation (STI), metal planarization, and other advanced applications. According to Miland Weling of VLSI Technology, speaking at a recent Solid State Technology-sponsored seminar in Santa Clara, CA, CMP pattern density effects are especially important in STI. Unlike conventional LOCOS isolation, STI leaves behind a highly planarized surface (Fig. 1), improving depth of field for subsequent lithography steps. Trench isolation also avoids "bird`s beak" encroachment by the field oxide, so transistors can be packed more closely.
Still, Weling reports, CMP may introduce new sources of variability in subsequent processes. If any oxide remains above the nitride layer after the CMP step, it will mask the nitride during the strip step. Furthermore, dishing of the isolation oxide regions (see "CMP dishing effects in shallow trench isolation," p. 187) may affect implant depth and degrade planarity.
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Figure 1. Shallow trench isolation process flow.
Howard Landis, from IBM Microelectronics noted that polish rate increases with pressure, and isolated features are subjected to more pressure than dense features. Since isolation regions can extend for many millimeters, pattern dependent effects make it very difficult to remove all the oxide from on top of the nitride (in dense regions) and still make sure that some nitride remains on isolated features.
To solve this problem, Landis suggested introducing dummy "fill" features in the isolation region. One fill approach uses an added resist layer to create additional, temporary, oxide features in large isolation regions. This two-mask process adds complexity, but the fill features cannot affect the finished device because they are removed during CMP (Fig. 2).
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Figure 2. Two-mask trench planarization process.
An alternative method simply adds dummy shapes inside the isolation regions to the isolation trench mask. These shapes remain on the wafer, so they could add parasitic capacitances if not properly designed.
As Landis said, "A good solution can fix more than one problem"; low metal pattern densities can cause problems during metal etch and ILD CMP. Landis found that dummy metal features can improve the ILD polish window, while adding negligible parasitic capacitance. - K.D.