Wafer dimensional analysis for chemical mechanical planarization
07/01/1997
Wafer dimensional analysis for chemical mechanical planarization
Y. Zhang, P. Golubtsov, L. Wagner, X. Yin, ADE Corp., Westwood, Massachusetts
P. Parikh, IPEC/Planar, Phoenix, Arizona
B. Stephenson, SGS-Thomson Microelectronics Inc., Phoenix, Arizona
In the past, several conventional metrology techniques have been employed for film thickness, roughness, and particle inspection in CMP equipment and process characterization. Recent joint efforts between device manufacturers and CMP equipment and metrology tool suppliers have shown that wafer dimensional analysis (WDA) via capacitive gauge is highly relevant for CMP process development and control.
Wafer dimensional measurement is one of the essential quality control steps in bulk silicon wafer manufacturing. It also has many applications in device fabrication, including wafer incoming inspection, thin-film stress diagnosis, thermal processing, photolithography and backgrinding [1].
Capacitive gauging tools can collect more than 16,000 data points on a 200-mm wafer in a little more than one minute. The resulting high-resolution maps of the wafer geometry illustrate equipment signatures and can help identify and diagnose process problems.
Experimental conditions
Two recent experiments studied the effects of wafer geometry on CMP. In the first, we measured total thickness variation (TTV) on fifteen 150-mm reclaimed test wafers with blanket thermal oxide films. After CMP, removed film WIWNU was correlated with pre-polish wafer TTV.
In the second experiment, we deposited a 1.5-?m blanket PETEOS film on a total of forty-five 200-mm prime wafers, divided into five groups. Varying RF power levels during deposition produced distinct wafer shapes, from highly concave to highly convex [2]. Three wafers from each group were then polished to thicknesses of 10, 8, and 6 k?. The process parameters and consumables were standard. Six 200-mm prime wafers with thermal oxide film, inserted in the CMP run at even intervals, supplied a reference for data normalization. All the wafers were polished on the same polish pad.
An optical film thickness measurement tool measured WIWNU and removal rate using a 49-point polar map with 6-mm edge exclusion. Wafer flatness, thickness, and bow were measured by a capacitive gauging tool before and after deposition, as well as after CMP. All the wafer maps presented in this article correspond to the same wafer at different process stages. The notch is at the bottom of the graphs and all measurement units are in microns.
Effect of wafer thickness variations
Pre-polish wafer quality has a strong effect on the CMP outcome [3] (Fig. 1). Film removal nonuniformity increases almost linearly with the pre-polish wafer TTV. Incoming wafer screening (especially of reclaimed test wafers) is necessary for rapid CMP ramp-up and material cost reduction. In several cases, pre-polish wafer dimensional measurements helped device fabs uncover this simple process deficiency after months of efforts in initial CMP process development and pilot production. Some CMP users have set an empirical TTV cut-off value of 5 ?m for 200-mm wafer pre-polish sorting.
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Figure 1. Removal uniformity vs. pre-polish wafer TTV.
Wafer flatness changes
Current techniques for CMP wafer planarity characterization are limited to either small area profiling or wafer diametric scans. True flatness characterization in a production setting requires a much faster and more efficient way to achieve full wafer area coverage.
Figures 2 and 3 compare site total indicator runout (STIR, 20 ? 20-mm site size) as reported by the capacitive gauge before and after CMP in the second experiment. STIR is the difference between the maximum and the minimum flatness deviation encountered at a particular site. These maps were constructed from the thousands of individual measurement points. While CMP removed the feature in the ten o`clock position on the pre-polish wafer, the STIR of several sites was actually worse after CMP.
To study this effect further, we constructed a composite STIR map for all wafers (Fig. 4) by overlaying the 45 individual flatness change maps to produce one overall "process signature" graph. Most sites on the wafers got better, especially around the wafer periphery, but some other sites consistently got worse. A careful analysis of such maps can improve tool setups, leading to higher yields and shorter learning periods. This approach is particularly enticing because it combines mathematical rigor with intuitive understanding.
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Figure 2. Wafer site flatness (STIR) before CMP.
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Figure 3. Wafer site flatness (STIR) after CMP.
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Figure 4. Composite STIR changes for all 45 wafers.
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Figure 5. Site flatness before and after CMP. Points lying below the 458 line represent sites with improved flatness after CMP.
Figure 5, based on the same data, describes the overall site flatness distribution for all 2205 sites (49 sites/wafer ? 45 wafers) before and after CMP. Again, the flatness of most of the sites improved after CMP (below the 458 line). Still, CMP does not lead to a tremendous improvement in relatively large scale flatness measures such as STIR. While the well-characterized micron-scale planarization effects contribute to major yield improvements, STIR data may help explain some of the mixed results observed by various CMP users.
For example, current CMP wafer planarity characterization focuses on a single die or a few dies using either profilometry or atomic force microscopy. These measurements can be location- and pattern-dependent. Local warpage or shape deformation may also contribute to thickness and roughness measurements if the wafer`s back surface is pulled down by a large vacuum chuck. Since the CMP process does not polish the back surface, any back-surface topography can "print through" to the wafer front surface and degrade the "effective" flatness seen by stepper optics. Imperfections of the stepper vacuum chuck and wafer local warp residuals also play a role.
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Figure 6. Wafer thickness changes after film deposit.
To quantify this study`s findings further, the site flatness requirement for advanced lithography was deemed to be equal to the desired design rule [4]. In other words, a site flatness of 0.25 ?m would be required for 0.25-?m lithography. After CMP, about 100 additional sites (among the 2205 sites studied) had site flatness values less than the 0.25-?m threshold. While this may not seem like an overwhelming result, it could translate into a large yield gain if the lithography improvement could be fully leveraged through the ensuing processes.
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Figure 7. Wafer thickness changes after CMP.
Wafer thickness changes
It is straightforward to construct thickness difference maps from the measurement data gathered during the second experiment. The wafers are aligned right on the measurement station, ensuring placement accuracy for both data sets. Thus, the user can look at high-resolution maps of oxide or metal films as they were added by the deposition tools, or thickness maps of the layer removed by CMP.
Adding a dielectric film to a wafer substrate will affect the total thickness value as reported by a capacitive gauge [5]; deposition of a dielectric film is electrically equivalent to adding a capacitor in series to an existing air gap capacitor. This study accounts for the dielectric effect in all relevant thickness measurements.
Capacitive gauging considers any and all thickness changes, including wafer backside effects due to surplus material deposition and carrier-induced effects that "print through" to the front of the wafer. This method aims to derive a fast, high-density map of wafer thickness changes; its aim is not to replace spectrophotometers, ellipsometers, or four point probes as highly accurate, point-based film measurement tools.
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Figure 8. Removal rate vs. wafer bow before CMP.
Figures 6 and 7 show the wafer thickness changes after PETEOS film deposition and after CMP processing, respectively. These maps clearly document the well-known annular removal nonuniformities observed with CMP processes. The localized features on the periphery of the wafer were removed by CMP. However, if the thickness variation shown in the first graph originated from the back of the wafer, then the CMP step would create a large dimple on the front of the wafer relative to the surface of the surrounding area.
Effect of wafer shape
Wafer shape is not static. It will change during the process, especially as a consequence of thin-film stress. Film stress is due to mismatch of the thermal expansion coefficients between a thin film and the underlying film or silicon substrate. Stress induced by film deposition can deform a wafer into a concave (negative bow) or a convex shape (positive bow). Stress can be calculated from the change in the wafer radius of curvature, which, in turn, is derived from the wafer warp values.
Some members of the CMP community believe that wafer warpage can be completely corrected by applying pressure to the wafer during polishing. However, since wafer warpage varies from wafer to wafer and process to process, consistency and flexibility are difficult to achieve with a constant pressure. Furthermore, some residual localized warpage persists after the wafer has been pressed against the polish platen. Figure 8 shows the relationship between CMP removal rate and pre-polish bow of wafers with PETEOS blanket films. The removal rate was normalized to the average removal rate for six thermal oxide wafers inserted at even intervals throughout the 45 PETEOS wafers. (CMP of thermal oxide is generally considered to be a standard process.) This behavior could be related to the scan pattern of optical film thickness measurement tools. The conventional 49-site polar map tends to report more points along a wafer periphery. In our study, the CMP tool polished the edge faster than the center on a concave wafer, so the reported removal rate was high. Pre-polish wafers with lower bow had lower WIWNU than wafers with higher bow.
Conclusion
WDA provides invaluable information about the effects of pre-polish wafer dimensional characteristics on CMP WIWNU and removal rate. Understanding wafer conditions beforehand can help to explain and even predict CMP results. In addition, WDA can estimate deposited or removed film thickness, especially for metal films where no obvious nondestructive metrology is available. Thus, this technique is attractive for both oxide and metal CMP monitoring.
Statistical tracking of wafer dimensional characteristics both before and after polishing drastically accelerates CMP process development and process control. It reduces test wafer usage and expedites polisher ramp-up. Such measurements are especially necessary given today`s tight wafer supply and steady industry growth.
Acknowledgment
The authors would like to express their appreciation to Russ Schlager, Bill Davis, Julie Collura, Tom Boardman, Mark Plemmons, Alex Belyaev, and Stephenia Volkey of ADE Corp.; and Karey Holland and Mike Bonsaver of IPEC/Planar for their suggestions and support of this work.
References
1. Y. Zhang, M.K. Jain, S. Nag, Advanced Metalization and Interconnect Systems for ULSI Applications in 1995, Portland, OR, Oct. 3-5, 1995.
2. Y. Zhang, et al., Proc. of VMIC, pp. 424-426, 1996.
3. Y. Zhang, et al., Proc. of CMP-MIC, pp. 90-96, 1996.
4. R. Goodall, H. Huff, SPIE Proc. of Metrology, Inspection and Process Control for Microlithography X, pp. 2725-2733, 1996.
5. K. Taylor, G. Bruton, D. Lou et al., 1994 IEEE/SEMI ASMC, pp. 225-228, 1994.
YUAN ZHANG received his MS degree in electrical engineering from the University of Rhode Island in 1994. He was a senior applications engineer with ADE Corp.
PETER GOLUBTSOV received his PhD degree in physics and mathematics from Moscow State University. He is a senior scientist with ADE Corp. under the SABIT exchange program. ADE Corp., 4125 Keller Springs Rd., Suite 128, Addison, TX 75244; ph 972/732-0074, fax 972/732-6704.
LUCIAN WAGNER received his BS degree in international economics from Georgetown University and his MBA from INSEAD, Fontainebleau, France. He was marketing manager for Device Fab Systems at ADE Corp. He is the owner of Simcom Corp.
XIAOMING YIN received his PhD degree in physics from the City University of New York in 1991. He is a senior engineer with ADE Corp.
PRABODH (PAUL) PARIKH received his MS degree in chemical engineering from Michigan State University, and his MBA degree from the University of Minnesota. He is a member of Process Technology at IPEC/Planar, where he is involved in development and applications of CMP and related technologies. He has more than 15 years of experience in semiconductor and electronics and is author or coauthor of several papers.
BRIAN STEPHENSON received his BS degree in engineering physics from Southwestern Oklahoma State University in 1991. He is a CMP section manager with SGS-Thomson Microelectronics Inc.