Advances in MCM ceramics
07/01/1997
TECHNOLOGY TOPICS
Advances in MCM ceramics
D.I. Amey, S.J. Horowitz, C.R.S. Needes, DuPont Photopolymer & Electronic Materials, Research Triangle Park, North Carolina
Semiconductor technology is advancing at a relentless pace, with increasing component and interconnect density, input/output (I/O) counts, and power dissipation placing more stringent demands on packaging technology. New packaging solutions must produce finer lines and smaller diameter vias with decreasing pitch, in processes that are robust and cost-effective.
The Semiconductor Industry Association (SIA) National Technology Roadmap for Semiconductors (NTRS) [1] predicts that the 0.18-?m chip generation (predicted to come online in the year 2001) will require 2000 I/O connections for chips between 500 and 800 mm2. Texas Instruments recently announced [2] that its CMOS process technology will shrink feature sizes and voltage levels 2-3 years ahead of NTRS timelines (last defined in 1994). Packaging and interconnect technology, particularly ceramic thick-film multichip module (MCM-C) processing, has kept pace with recent IC advances.
New ceramic thick-film materials and processes have been developed to extend the capability of conventional MCM-C technology. High-density circuits that use the unique features of these materials are transitioning from R&D to manufacturing. This article reviews these materials and their processing (including Diffusion Patterned, photo-imageable, and tape-cast systems) against a packaging density roadmap. Compatible materials for forming integral buried resistors and capacitors in MCM-Cs are also described. Advanced designs that take advantage of these new materials systems are discussed.
Conventional MCM-C
Advances in ICs drive packaging technology by increasing the number of I/O connections, the operating speeds, and the thermal dissipation requirements. Packaging interconnections must also accommodate passive components required for EMI reduction, filter circuits, terminations, and impedance matching. Passive components can occupy significant substrate area.
Burying resistors and capacitors within the multilayer interconnect structure frees more substrate area for active devices, thereby increasing circuit density and/or functionality. Increasing circuit density results in more circuits/substrate and a correspondingly lower manufacturing cost/substrate.
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Figure 1. In the Diffusion Patterning process, resolution is nearly doubled because the thin imaging paste does not spread during printing.
Packaging density is also driven by the need to assemble bare ICs. Ceramic thick-film materials are compatible with a wide variety of bare-chip assembly technologies, including direct wire-bonding or solder attachment.
The robust performance of conventional thick-film ceramic technology (including compatibility with environmental extremes, and high power dissipation) results in many successful high-volume automotive, consumer, and telecommunications MCM-C designs. However, when <250-?m vias and >5 metal layers are specified, lower yields and higher manufacturing costs limit conventional MCM-C designs.
Standard thick-film materials spread during printing, so that via cross-sections are fluted with small bases and much larger diameter tops. This shape limits minimum via pitch to 500 ?m and via diameter to 250 ?m in high volume manufacturing.
Conventional ceramic thick-film processing effectively limits MCM-Cs to 2-3 metal layers for high volume production. Higher layer counts (6-8 metal layers) have generally been limited to low-volume, high-value applications.
Newer MCM-C materials
DuPont has developed new thick-film ceramic families to reduce the minimum feature size, and simplify the processing of MCM-C interconnects.
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Figure 2. The photo-imageable process using Fodel photo-imageable materials can produce both conductor and insulator layers.
Diffusion Patterning. Diffusion Patterning [3-6] is based on a chemical reaction between a dried dielectric film and an imaging paste that is screen printed onto its surface. The position of the imaging paste defines the position of vias (Fig. 1). This process extends the via resolution of conventional thick-film dielectrics (125-?m vias on a 250-?m pitch were demonstrated in volume production), since the relatively thin imaging paste can be printed without substantial spreading.
The process is aqueous and environmentally safe, but is currently only established to image dielectric layers (metal layers require a different process). Since it uses standard thick-film production equipment, Diffusion Patterning requires minimal incremental investment for an existing facility. The process was used to produce remote terminals for a military avionics application with 43% of the substrate surface occupied by silicon (a very high ratio).
Photo-imageable. Photosensitive polymers are incorporated into "Fodel" photo-imageable materials [7, 8], so that dielectric or conductor features are formed by UV light exposure and aqueous development (Fig. 2). Photo-imageable dielectrics can form 75-?m vias on a 125-?m pitch, and photo-imageable conductors can form 50-?m lines on a 100-?m pitch. A 144 I/O, four metal layer SPARC-processor substrate built with the photo-imageable process (Fig. 3) achieved a silicon to substrate ratio of 50% with a via pitch of 150 ?m (6 mil) [8].
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Figure 3. SPARC processor package produced with photo-imageable MCM-C process. (Photo courtesy of Dassault, France.)
Photo-imageable gold and silver conductors have lower attenuation than thin-film gold on the same 96% alumina substrates, over the frequency range 0.5-20 GHz [15, 16]. The photo-imageable gold and silver conductors on these substrates had approximately the same attenuation and loss as more costly PTFE laminates.
Low temperature cofired ceramic. Low temperature cofired ceramic (LTCC) technology [9] is based on "Green Tape" dielectric thick-film tape-casting (Fig. 4) instead of screen printing. "Green" (unfired) dielectric tape is blanked to size, and registration holes are punched. After punching or drilling to form vias, conductor lines are screen printed on the tape.
When all layers have been punched and printed, they are registered, laminated, and cofired. Since the cofire process requires fewer firing steps and allows for the inspection of punched printed layers prior to lamination, it can produce a greater number of layers with higher final yield than other MCM-C processes. A variety of gold, silver, and copper interconnects have been incorporated into LTCC structures.
A read/write amplifier circuit, manufactured by CTS for a high capacity Seagate disk-drive, used tape-cast ceramics (Fig. 5). The high frequency performance of tape-cast LTCC materials [15, 16] increases data transfer rates. Tape-cast multilayers have lower dielectric loss than conventional organic laminates.
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Figure 4. Individual "Green" tape-cast layers are patterned and then stacked together for simultaneous firing in the low-temperature cofired ceramic (LTCC) process.
Buried passive components
Conventional thick-film dielectrics are incompatible with buried resistors, as the glass and conductive phases inter-diffuse during refiring to produce large shifts in resistance and temperature coefficient of resistance (TCR). These shifts can impair circuit function, particularly in circuits that require the precise values of trimmed resistors.
Similar interactions occur between conventional thick-film materials and buried high dielectric-constant capacitors. New materials that interact in a controlled way during re-firing (Fig. 6) minimize these problematic interactions [10].
These new materials can be laser trimmed after initial firing. Re-fired multilayer resistor values shift <10%, with tight distributions of resistance. In addition, these materials have excellent post-trim environmental stability, and very high temperature stability (~400?C), allowing automotive under-the-hood and on-engine applications. Buried capacitors have been reported in tape-cast and other LTCC systems [11, 12].
The density capability [13] of the new MCM-C materials (cm of conductor/cm2 of board area) can be compared with conventional MCM-C, PWB laminates, and MCM thin-film deposition (MCM-D) [14]. Diffusion-patterning and tape-cast systems have moderate capabilities between PWB and MCM-D, while photo-imageable layers demonstrate densities comparable to MCM-D. Fewer signal layers result in higher yields and lower costs. Another valuable density metric is the packaging density (silicon area to substrate area ratio) as a function of minimum feature size capability (Fig. 7).
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Figure 5. Read/write amplifier made using LTCC process. (Photo courtesy of CTS Microelectronics.)
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Figure 6. Buried resistor and capacitor construction allows more of the substrate surface to be reserved for ICs.
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Figure 7. Minimum design characteristic for various MCMs as a function of silicon-to-substrate area ratio. A higher ratio indicates a more efficient layout.
Summary
Ceramic interconnect technology has been used in the electronics industry for over 30 years. Despite consistent predictions of its demise, ceramic usage continues to grow and the technology continues to offer advantages in both high performance (digital, wireless, microwave) and cost-sensitive (automotive) applications.
Both photo-imageable and Diffusion Patterned ceramics are viable alternatives to replace MCM-D in many applications. MCM-Cs produced with photo-imageable and Diffusion Patterned films cost only 55% and 46% (respectively) of the cost of comparable MCM-Ds [17].
New generations of MCM-Cs were developed for, and are currently being adopted by, volume manufacturing and high I/O applications. Modeling shows that these new materials offer very attractive cost-performance tradeoffs for many applications. The technology is extensible, reliable, and cost effective. A broad thick-film ceramic infrastructure allows low risk entry into the world of MCMs.
Acknowledgments
The authors gratefully acknowledge the contributions of R.C. Mason, J.D. Smith, and T.R. Suess, members of the technical staff at the DuPont Electronic Materials Technology Center, Research Triangle Park, NC.
"Diffusion Patterning" is a trademark, and "Fodel" and "Green Tape" are registered trademarks of DuPont. "SPARC" is a trademark of Sun Microsystems.
References
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For further information, contact: S.J. Horowitz, DuPont Electronic Materials, Research Triangle Park, NC 27709; ph 919/248-5752; fax 919/248-5715.