Low-temperature polysilicon reshapes FPD production
07/01/1997
Low-temperature polysilicon reshapes FPD production
Julian G. Blake, Michael C. King, James D. Stevens III, Eaton Flat Panel Equipment, Beverly, Massachusetts, Ross Young, DisplaySearch, Austin, Texas
Compared to amorphous silicon, polysilicon has higher electron and hole mobilities. Device design rules can shrink, self-alignment features are possible, and pixel charging time decreases, facilitating higher gray scale, color, and real-time video. Pixel aperture ratios become larger, producing brighter and lower power displays. The smaller size and improved performance of polysilicon thin-film transistors (TFTs) also make them suitable for higher-definition displays.
Moreover, better TFT performance may be coupled with lower panel-manufacturing costs. Driver circuitry, which typically accounts for 5-30% of the total panel cost, can be integrated into a polysilicon display. Fabricating the drivers directly on the glass eliminates the traditional tape automated bonding driver package, simplifies the display module process, and slashes module process equipment costs. Integration not only reduces costs but also increases reliability and module process throughput because fewer interconnects are needed.
LTPS TFTs can be fabricated with either bottom-gate or top-gate NMOS processes. The driver circuitry, however, is fabricated by top-gate CMOS. Figure 1 shows a top-gate LTPS pixel TFT. First, a layer of CVD amorphous silicon is converted to polysilicon. CVD SiO2 and plasma CVD SiNx, deposited over the outlined transistor, form the gate-dielectric layers. The metal gate is then deposited and etched. Next, the phosphorus source/drain implants use the gate pattern as a mask. Either extended annealing in hydrogen or an excimer laser activates the implant. Sputtered aluminum, deposited in vias etched through the gate, forms source/drain contacts and serves as the data/address lines. Transparent sputtered ITO forms the electrode area. Finally, the device receives a SiNx passivation layer. This process is "fully self-aligned" because the gate serves directly as the source/drain implant mask.
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Figure 1. Cross section of a typical LTPS TFT.
LTPS devices typically have mobilities of 50-100 cm2/V-sec, leakage currents of 1-10 pA, and n-channel threshold voltages of 1-2 V. Figure 2 compares process flows for amorphous silicon and LTPS TFTs. Integrated on-glass CMOS driver circuits require a more complicated process flow with added ion implant and photolithography steps.
LTPS manufacturing challenges
LTPS must overcome a number of significant production challenges to realize these benefits. Typically, all processing must be conducted at 4508C or lower in order to use low-cost glass substrates. The LTPS process also differs from the amorphous silicon process in several significant respects; reduced hydrogen content amorphous silicon CVD, annealing equipment, ion implantation doping equipment, a new gate-dielectric CVD process, finer resolution lithography equipment, and hydrogenation equipment will all be required.
Hydrogenation. Hydrogen passivation is a key technology for polysilicon TFTs. Hydrogen ties up dangling bonds between grains and at the interface with the gate dielectric, allowing high mobilities, low threshold slopes and leakage currents, and improved device uniformity. Possible approaches to hydrogen passivation include parallel plate hydrogen plasma exposure, solid-source diffusion, and ion implantation. Hydrogen plasma exposure delivers the best TFT performance and good uniformity, but requires several hours of process time. Alternative approaches with high-density plasma, such as electron cyclotron resonance (ECR) and transformer-coupled plasma, are under development and could significantly reduce this process time.
Gate-dielectric deposition. LTPS manufacturers need a low-temperature (<4008C) gate dielectric with the desirable characteristics of a thermally grown oxide. SiO2 has not been used as a gate dielectric in bottom-gate amorphous silicon production, so top-gate LTPS manufacturing will require a new process. Thickness uniformity requirements for polysilicon gate dielectrics are very stringent - 6-7% compared to the 15% uniformity expected of the SiNx gate dielectric in amorphous silicon displays [1]. The SiO2 gate dielectric is typically 100-120 nm thick and must be deposited in about 1 min. Several different process approaches have been demonstrated, including LPCVD, atmospheric pressure chemical vapor deposition (APCVD), physical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), and ECR. Critical parameters include electrical characteristics, step coverage, film-thickness uniformity, and process temperature.
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Figure 2. Process comparison: a) amorphous silicon TFT vs. b) LTPS TFT.
The table displays the various alternatives and their respective performance. PECVD with SiH4/N2 or TEOS meets all the requirements, while PECVD with TEOS provides better step coverage.
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Both AKT and ULVAC have introduced TEOS processes in their PECVD systems. ULVAC has demonstrated SiO2 film quality comparable to thermal oxide films. It claims that its higher-frequency excitation (27.12 MHz vs. 13.56 MHz) yields higher plasma density, higher deposition rates, a lower thermal load, and fewer cleaning cycles, thus allowing superior throughput, electrical characteristics, and uptime. Existing amorphous silicon PECVD systems can be modified for TEOS use by modifying the gas delivery system [2]. For the future, systems must maintain film-thickness uniformity, increase deposition rates, and achieve good electrical properties, while keeping process temperatures low and minimizing particulates.
Photolithography. The limitations of today`s LCD lithographic equipment match the 5.0-?m design rule limits imposed by the low carrier mobility of amorphous silicon. The higher mobility of polysilicon permits tighter TFT design rules with narrower channels. Minimum resolutions of 1.0 or even submicron dimensions could be used. Submicron lithographic techniques for semiconductor fabrication are not readily transferable to AMLCD manufacturing, which requires larger device areas and uses large glass substrates lacking the flatness achievable on silicon wafers. LTPS lithography must also compensate for glass compaction in high-temperature process steps.
Exposure tools take longer and cost more to develop than other FPD manufacturing equipment. Due to the short and unpredictable time between equipment generations, companies have been reluctant to invest heavily in this area. Today, exposure tools for AMLCD manufacturing are supplied by Canon, Nikon, and MRS Technology. Canon`s FPD equipment uses a 1:1 optical scanning technology capable of exposing a complete display in a single scan. Nikon and MRS Technology use an optical step-and-repeat protocol capable of precise stitching of multiple images. The higher-resolution requirements of LTPS favor optical steppers.
In the foreseeable future, practical lithographic performance will settle in the 1.0-2.0 ?m range. This performance is achievable, with some loss of throughput, by substituting smaller-field, higher-resolution lenses into existing equipment. Exposure capability down to 1.0 ?m is presently available from MRS Technology and Nikon. High-resolution, high-throughput photolithography will have to wait for new generations of lithographic equipment.
Ion doping. Three primary ion-doping methods are used for flat panels today. The first uses conventional high-current, spinning disk implanters designed for silicon wafer fabrication. These expensive tools are capable of very high throughput (220 substrates/hr mechanical limits are typical) and very tight process control, including keeping the substrate cool during high-dose, high-energy implants. Since substrate size is only 200-mm dia., increasing to 300 mm this year, this equipment is only appropriate for high-temperature polysilicon displays on small quartz substrates. These tools also use mass analysis, making co-implantation of dopant and hydrogen impossible.
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Figure 3. Schematic illustration of the Eaton ORion NV6072. The machine is designed to process panels as large as 600 ? 720 mm in area and only 0.7-mm thick.
The second approach, often called an ion shower, employs an ion source larger in size than the panel to be implanted. Ions are extracted and accelerated through a grid and implanted without mass analysis. Hydrogen is co-implanted with the dopant by using PH3 or B2H6 source gases. While large panels can be implanted, each substrate size increase requires a larger ion source. Ion shower tools typically scan the panel during implant to insure good dose uniformity. Though this motion complicates panel handling, it is still much simpler than a spinning disk. The extremely large plasma electrode transparency of the ion source in this design restricts the range of usable gas pressures. Low-dose implants for threshold voltage (Vt) adjustment and lightly doped drain (LDD) formation require extreme dilution of the dopant gas with hydrogen. Since the amount of dopant actually ionized, and hence the dose rate, depends critically on the plasma conditions, dose control for low-dose implants can be extremely difficult. Finally, the throughput of these ion shower systems tends to be low.
Recently, Eaton Flat Panel began shipment of a new flat panel implant tool that provides high throughput (in excess of 60 plates/hr), precise dose uniformity, and high repeatability over the range 5 ? 1011 ions/cm2 to 5 ? 1015 ions/cm2, while keeping the glass temperature below 1208C [3, 4]. This tool (Fig. 3) uses a ribbon beam with 1-D scanning of the glass. The smaller transparency of the extraction electrode compared to that of an ion shower allows operation over a wider range of plasma densities. Thus, a wide range of implant doses can be achieved without diluting the source gas. Because the panel scans past the ion beam, the ion source remains on continuously, allowing for more stable operation. The ion beam current density, and hence energy density, is somewhat higher than in an ion shower system. Still, thermal modeling shows that as long as the width of the ion beam is larger than 15 cm, the maximum temperature of the glass surface does not appreciably exceed that experienced with an ion shower.
Implant activation. For a transistor to work effectively, the source and drain contacts must have relatively low resistance. Low sheet resistance (Rs) in the source and drain contact regions, in turn, requires fairly complete activation of the high-dose source and drain implants. Activation allows the dopant atoms to assume substitutional sites and heals damage to the silicon lattice. In conventional CMOS processing, this step is performed by either a furnace anneal or by rapid thermal processing (RTP). However, either of these steps requires temperatures well beyond those allowable for commonly used glasses. Furthermore, high-temperature activation will drive out hydrogen incorporated during the implant, forcing a final hydrogenation step.
Several solutions have been proposed, but none is entirely successful. Laser annealing can provide almost complete activation of the implant, since it heats the silicon layer without heating the glass. Present equipment is not robust, however, and throughput is low.
Furnace annealing at temperatures of 5008C for several hours provides less complete activation than laser annealing. Implanting at elevated temperatures (typically 200-2508C) provides a degree of self-activation that can result in satisfactory sheet resistance. A hard mask must be used, though, increasing the number of processing steps. Manufacturers of AMLCDs are using many variations of these approaches; none is a clear winner at this point.
Conclusion
Most AMLCD manufacturers are directing considerable effort toward development of LTPS technology. A few manufacturers are presently producing small-and medium-size displays using LTPS because it offers not only a performance advantage over amorphous silicon but also a significant cost advantage. By 2000, almost all high-resolution AMLCDs smaller than 6 in. will use LTPS. The impact on the notebook and LCD monitor markets will depend on the success of process and tool development. Several major AMLCD notebook display manufacturers have started development programs aimed at succeeding in this market segment, and it is expected that by 2000, LTPS will have gained a foothold.n
Acknowledgment
The authors thank Daniel Ferrin of Eaton Semiconductor Equipment Operations for the preparation of the graphs and drawings, and Mark Lucas, MRS Technology, and Fred Kahn, Kahn International, for manuscript review and suggestions.
References
1. DisplaySearch, Interview with Kam Law, AKT, February 1997.
2. K. Ito et al., Low Temperature Mass Production Technology for Poly-Si TFT, ULVAC Japan White Paper, 1996.
3. M. Sato et al., Proceedings AM-LCD `96, pp. 353-356, November 1996.
4. K. H. Lee et al., Proceedings SEMICON Korea `97 FPD Technology Conference, pp. 99-110, February 1997.
JULIAN G. BLAKE received his AB degree from Amherst College, and his MAT and PhD degrees from Harvard University, where he worked on the optical properties of sputtered aSi:H and aSiGe:H films. He joined Eaton Corp. in 1984, and has been involved in process development and machine design of thin-film deposition, rapid thermal processing, and ion implant products. Blake is presently the technical director for Eaton Flat Panel Equipment, responsible for thin-film transistor process development and machine design of ion implanter products for flat panel displays.
MICHAEL C. KING received his PhD degree in solid state physics from Carnegie-Mellon University. He is currently GM of the Flat Panel Equipment Division at Eaton Corp. Prior to joining Eaton, King was VP of technology at MRS Technology, VP of R&D at Summit Technology, founder and VP of Ion Microfabrication Systems Inc., VP of technical marketing at GCA Corp., technical director of the Microlithography Division at Perkin-Elmer Corp., and a member of the technical staff at Bell Telephone Labs.
JAMES D. STEVENS III received his BS degree in management engineering from Rensselaer Polytechnic Institute, and his MS in operations research and applied statistics from Union College, Schenectady, NY. He joined Eaton Corp.`s Flat Panel Equipment Division as worldwide sales and marketing manager in August 1995. Prior to joining Eaton, Stevens served as director of marketing for Rodel. Eaton Flat Panel Equipment, 108 Cherry Hill Drive, Beverly, MA 01915; ph 508/524-9229, fax 508/524-9224, e-mail [email protected].
ROSS YOUNG received his education at Japan`s Tohoku University and the University of California at San Diego`s Graduate School of International Relations and Pacific Studies. He founded the FPD market research firm DisplaySearch in early 1996. Prior to founding DisplaySearch, Young held senior marketing positions in the FPD manufacturing equipment, FPD materials, and semiconductor equipment industries.