Electrochecmical Planarization of ULSI copper
06/01/1997
Electrochemical planarization of ULSI copper
Robert J. Contolini, Steven T. Mayer, Robert T. Graff, Lisa Tarte,
Anthony F. Bernhardt, Lawrence Livermore National Laboratory, Livermore, California
Electrochemical planarization (ECP) of copper has been demonstrated on ULSI damascene features. The basic process involves two stages: cathodic plating into vias and trenches, and anodic electropolishing down to a seed layer. Resulting metal structures are void-free. A semi-automatic aqueous processing system, based upon an easily controlled chemistry, has achieved reasonable uniformities. This simple process could be much less expensive than alternatives for =0.25-?m interconnects.
Copper is likely to replace aluminum for interconnect metallization in future integrated circuits [1]. The longest signal lines on a chip tend to limit the clock frequency because of the time - given by the line resistance times its capacitance (R ? C or "RC") - required for the signal to bring the line up to the switching voltage of the driven gate.
Copper has lower resistivity than aluminum (1.8 vs. 3.7?W-cm), which reduces the resistance factor in the RC delay. In interconnect layers that do not limit the clock frequency, copper would also permit smaller traces and finer pitch compared to aluminum. Furthermore, copper is less subject to electromigration than aluminum, reducing the risk of long-term IC failure.
Metal trace widths on the lowest metal layer have been shrinking to accommodate higher densities of transistors, while trace thickness has been reduced much more slowly to keep trace resistance (directly proportional to cross-sectional area) from rising more than necessary. Traces on future generations of integrated circuits will have an aspect ratio (thickness divided by width) exceeding 2:1 in 1998 and 3:1 in 2004 [2]. Metal traces and vias with high aspect ratios present special processing problems that may be addressed more readily with copper than with aluminum.
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Figure 1. a), b) Electrochemical planarization uses a relatively simple process flow to complete damascene metallization. Since a continuous barrier layer is required for deposition, this layer must be removed c) with a wet-etch or CMP after electropolishing has removed the bulk of surface copper.
The process ECP, involving copper electroplating followed by electropolishing [3], results in a very flat surface containing embedded, high-aspect-ratio conductors. Copper ECP has been used to metallize silicon circuit boards for multichip modules and ULSI interconnects [4, 5]. Planarization occurs without a particle slurry and with a significantly reduced waste stream. The copper electroplating and electropolishing processes have shown a thickness uniformity of better than ? 2% 3 s across 100-mm-dia. Si wafers and across 125-mm2 substrates. The equipment required for ECP is relatively inexpensive and uses simple chemicals that can be recovered and recycled.
Comparison of ECP to conventional planarization
A conventional damascene metal planarization scheme for copper starts with physical vapor deposition (PVD) or chemical vapor deposition (CVD) of a metal barrier layer. Copper is then deposited into patterned features with a blanket metal PVD or CVD process. High-aspect-ratio structures may be difficult to fill with PVD-based processes (even using reflow), and CVD processes use relatively expensive and hard-to-control organometallic precursors. A CMP tool, using an abrasive chemical slurry solution in combination with a polishing pad and platen, chemically and mechanically polishes away the copper layer on top of dielectric structures [6], leaving behind embedded conductors. Finally, a post-CMP cleaning process is necessary to remove particles.
The copper ECP process is considerably simpler (Fig. 1). A metal barrier layer plus a copper seed layer are deposited (by PVD or CVD) prior to electroplating. The copper is then electroplated in an aqueous solution with the substrate metal surface as the negative electrode of the electrochemical cell. An electropolishing tool removes most of the copper above trenches/vias, using a particle-free liquid electrolyte with the substrate metal surface as the positive electrode of an electrochemical cell. After the majority of the metal is electropolished away, the thin residual seed metal is wet etched and rinsed.
Six years ago, ECP was performed on samples only 10 mm in diameter with pattern dimensions of 5-10 ?m. Our group has since planarized samples as large as 250 mm, and has deposited copper into submicron patterns. Copper and gold planarization have used ECP with various oxide and polyimide dielectric layers. The electropolishing portion of ECP is applicable to any metal with any dielectric that is chemically inert in the electropolishing solutions.
Single-wafer flow electroplating
Copper is electroplated in a patented single-wafer flow electroplating cell (Fig. 2). A sulfuric-acid copper-sulfate chemical system without organic additives results in a robust plating solution that requires minimal adjustment for months. Concentrations are fine-tuned by measuring pH, conductivity, and the visible absorbance.
Solution flows up through the inner cell, through the porous counter electrode, across the surface of the rotating sample, and into the outer cell, from which it is pumped, heated/cooled, and filtered before returning to the inner cell. A reference electrode, inserted in a tube near the sample surface, gives a more accurate voltage measurement in the cell. Plating rates are 0.1-1.0 ?m/min. A specialized pulsed waveform is supplied across the cell by a standard electrochemical power supply. Coulometry (the measurement of charge passed through the electrochemical cell) helps determine the plating endpoint. The resistivity of the electroplated copper is 1.85 ?W-cm.
The chemistry of copper electroplating is rather simple. The copper sulfate in the highly acidified aqueous solution forms ions of Cu2+ and SO42-. At the negative electrode, which in this case is the sample wafer, the Cu2+ ions are "reduced" to Cu metal, depositing with excellent adhesion on the sample surface. At the positive electrode, the copper mesh, Cu metal dissolves into solution as Cu2+ ions.
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Figure 2. Schematic of the electroplating system. The ability to perform metal gap-filling is determined by the waveform shape.
Early results from galvanostatic (constant current, without a reference electrode) plating of copper on 5.5-?m-deep trenches were not encouraging (Fig. 3a). Trenches that were plated at 0.5 ?m/min had large 3-?m voids in the 6-?m-wide trenches. Voids form because of faster plating at the top sharp edges of trenches compared to the bottoms. Higher primary and tertiary current densities occur at sharp edges, and hence higher deposition rates.
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Figure 3. SEM cross-sections of large (6-?m wide) test structures show the benefit of optimally tuned pulsed waveform deposition: a) a large void results from 0.55 ?m/min. galvanostatic (constant current) plating, b) while a 1 msec on/1 msec off current pulsing achieves 0.5 ?m/min. deposition without a void.
During electroplating, a diffusion boundry layer is established above the sample, where the Cu concentration trails off from the bulk. This boundry layer thickness is typically several microns. For a diffusion layer thickness that is larger than the pattern dimension, the copper ion density is higher at trench top edges than at bottoms, and a higher deposition rate is expected at the top. Note also the "cleft," or slight depression, at the top of the filled conductor trenches. Even after a 6- to 8-?m thickness of plating, a 2- to 3-?m-deep cleft remained above a 10-?m-wide, 5.5-?m-deep trench.
Pulsed voltage plating techniques reduce the formation of voids because the rate of metal deposition deep inside a trench becomes nearly the same as the rate at the upper portion [7]. With an optimally shaped voltage pulse (both amplitude and temporal shape), most of the voltage drop occurs at the sample surface rather than within the solution.
Figure 3b shows a 6-?m-wide trench that was 1 ms on/1 ms off voltage pulse-plated at -0.20 V (with respect to a copper wire reference electrode). Although the deposition rate is nearly the same as the galvanostatic plating shown in Fig. 3a, voids do not occur. SEM cross-sections of 0.35-?m, 2.4:1 aspect ratio copper electroplated trenches (Fig. 4) show that ULSI damascene structures can be filled without voids by using appropriately shaped waveforms [3].
Globally uniform metal deposition is important for the success of the electrochemical planarization process. For a 100-mm wafer, a ?1.8% 3 s thickness uniformity (of the mean) has been achieved. For a square 175-mm diagonal glass sample, a ?1.9% 3 s thickness uniformity has been achieved. Recent results on 150-mm and larger wafers show uniformities of less than 3% 1 s.
Single-wafer flow electropolishing
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Figure 4. SEM cross-section of a 0.35 ?m, 2.6:1 trench filled void-free with electroplated copper.
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Figure 5. Schematic of the electropolishing system. Transparent electrolyte allows for a variety of external endpoint techniques
Electropolishing [8] electrochemically removes metal in a manner that dissolves protruding surface features at a faster rate than features that are in valleys or crevices [9, 10]. The electropolishing process is a particular case of anodic dissolution in which a viscous liquid electrolyte is used in the electropolishing cell. The metal on the highest, sharpest surface features, which stick up through the thick boundary layer, dissolves more rapidly than metal deep in crevices (such as the metal in buried conductors). Nonlinear solute diffusion constants [11] also help to explain the micro-leveling action of electropolishing.
Constant-potential electropolishing (Fig. 5) removes the excess metal in the field regions of the sample at 0.25-1.0 ?m/min [12]. A computer-controlled, high-current power supply maintains the cell voltage in the "electropolishing regime" of the current-voltage curve, while a coulometer measures the charge passed through the sample. The positively biased sample rotates near the top of the phosphoric acid electropolishing solution, while the negatively biased counter electrode is a screen surrounding the inner cell. Solution flows from the inner cell through a filter and heat exchanger, and is pumped into the outer cell. Because the sample is in a clear solution, one can easily view the surface during the electropolishing, thereby providing convenient visual monitoring for endpoint determination, defect formation, and pattern changes as electropolishing proceeds.
Figure 6 plots the current density as a function of time for a part in which the voltage was set to 1.35 V (with respect to a copper reference electrode) at time zero. This voltage is not completely corrected for solution-resistive potential drop, but is most accurate when the reference electrode is very close to the anode. Initially the current was large, and about two minutes elapsed before a steady-state current was reached.
During this initial transient period, the mass transport boundary layer is being set up. In contrast to that required for ULSI electroplating, optimal electropolishing boundry layers are several orders of magnitude thicker. Actual electropolishing does not begin until steady state current is established (the surface appears optically polished at this point) across the boundary layer. The cell voltage (counter electrode to working electrode voltage) also undergoes a similar transient decay.
By fixing either the cell`s current or voltage during the entire process (without using a reference electrode), electropolishing may still occur, but it is likely that the system will evolve oxygen. The gas bubbles thus generated will cause severe etch pits in the sample metal surface.
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Figure 6. Current density as a function of time in the electropolishing system. Actual electropolishing does not begin until the current is steady state. The voltage was set to 1.35 V.
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Figure 7. A 500-?m profilometer trace across an unpatterned surface plated with 8 ?m of copper a) before and b) after electropolishing. The average peak-to-valley height drops from about 1 ?m to less than 0.05 ?m.
Numerical simulations of the potential distribution inside several geometrical configurations of electropolishing apparatus have established the optimum physical layout. The configurations were evaluated with regard to the effect on the spatial current distribution of the anode and cathode.
The actual current distribution in the electropolishing apparatus (confirmed by experimental results) is significantly better than that predicted by the simulations. As long as the solution resistance is reasonably uniform (primary current distribution), the effects of electron transfer resistances (secondary current distribution) and diffusion control (tertiary current distribution) will not prevent a highly uniform polishing process from being established.
To preclude rapid overetching of the embedded conductors, the electropolishing is terminated when the metal first begins to clear. Endpoint is determined either visually, by use of coulometry, by current monitoring, or based on time. The thin residual metal is normally removed by a wet etch. Samples up to 250 mm in the largest dimension were successfully electropolished.
The micro-leveling action of electropolishing was demonstrated across a distance of 500 ?m. A profilometer trace across an unpatterned surface plated with 8 ?m of copper (Fig. 7a) shows an average peak-to-valley height of about 1 ?m. After electropolishing down to a final copper thickness of 0.25 ?m, the average peak-to-valley height is less than 0.05 ?m (Fig. 7b).
Macroscopically, the copper removal is quite uniform across 100- and 175-mm samples. Data from a 175-mm square sample electroplated to a thickness of 23 ?m of copper and subsequently electropolished to 1-?m thickness shows that copper was removed with a uniformity of ?2.5% 2 s across the sample.
ECP planarization was performed on ULSI samples having 0.8-?m-wide vias (Fig. 8) and trenches. Samples were copper electroplated, electropolished, and wet etched. The field metal was entirely removed, leaving embedded vias and conductor traces. In principle, a CMP process could remove the residual copper following electropolishing. A semiautomatic ECP system was demonstrated, including two cleaning stations, two electroplating stations, and one electropolishing station.
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Figure 8. ULSI samples with 0.8-?m-wide vias after copper electroplating, electropolishing, and wet etching.
Conclusion
ECP offers unique advantages over previous planarization techniques. Pulsed voltage electroplating produces low resistivity copper conductors from a simplified chemical plating bath that is quite robust for long periods of time. Packaging applications, with relatively relaxed design rules, allow for the highest controllable plating rate (1 ?m/min) using either single-substrate or multisubstrate cells on a frame. Electroplating of ULSI patterned samples is more suited to a single-wafer cell.
The lack of organic additives results in significantly less hazardous waste than from conventional copper plating baths. Electropolishing at a rate of up to 1 ?m/min uses multiple endpoint control: coulometry, time, current, and visual techniques. Electropolishing has significantly less hazardous waste accumulation than CMP, since the former generates no slurry needing disposal. Copper, which dissolves in the electropolishing bath, electroplates in the cathode compartment, where it can be removed easily and recycled. The electropolishing chemistry is very simple: phosphoric acid with no additives.
We have shown that copper ECP effectively metallizes and planarizes first-level ULSI metal and multichip module size features. The uniformities of both the electroplating and electropolishing processes are within ?3% 1 s across a 150-mm wafer. ECP can save process steps and time in conjunction with damascene processes (now used in ULSI fabrication). The first implementation of copper ECP may be to metallize and planarize, with CMP used to remove the last seed layer trace. In the future, the electropolishing portion of ECP could be an alternative to CMP.
Acknowledgments
We would like to thank Mark Scrivener (now at Integrated Device Technologies), Mercedes Dickerson, and Thomas Clark of LLNL for their help with the software development for the electrochemical system; Intel Corp., especially Neal Cox, for providing 150-mm patterned samples and FIB cross-sections, as well as financial assistance to upgrade the electroplating system; George Georgiou, of ATT Bell Laboratories for patterned samples; and Shyama Mukherjee of IBM (now at Moltech Corp.) for 250-mm electropolishing samples and financial assistance.
The work was performed under the auspices of the US Department of Energy by Lawrence Livermore National Laboratory (LLNL) under contract no. W-7405-Eng-48.
References
1. "Special issue on copper interconnects," Thin Solid Films, 262, no. 1, 2, June 1995.
2. Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, p. 98, 1994.
3. R.J. Contolini, A.F. Bernhardt, S.T. Mayer, "Electrochemical Planarization for Multilevel Metallization, J. Electrochem. Soc., 141, no. 9, p. 2503, 1994.
4. R.J. Contolini, et al., "Electroplating Process for Sub-Half-Micron ULSI Structures," 1995 VLSI Multilevel Interconnection Conference, p. 322, 1995.
5. A. F. Bernhardt, et al., "Multichip Packaging for Very-High-Speed Digital Systems," Appl. Surf. Sci., 46, p. 121, 1990.
6. J.M. Steigerwald, e al., "Electrochemical Potential Measurements during the Chemical-Mechanical Polishing of Copper Thin Films," J. Electrochem. Soc., 142, no. 7, p. 2379, 1995.
7. U. Landau, "Seventh Workshop on Electrochemical Engineering," May 2-6, 1988, Case Western Reserve University, Cleveland, Ohio.
8. J. Edwards, "The Mechanism of Electropolishing of Copper in Phosphoric Acid Solutions," J. Electrochem. Soc., 100, no. 8, p. 223C, 1953.
9. P.V. Shigolev, "Electrolytic and Chemical Polishing of Metals," Freund Publishing House, Tel-Aviv, Israel, 1974.
10. S.H. Glarum, J.H. Marshall, "The Anodic Dissolution of Copper into Phosphoric Acid, I. Voltammetric and Oscillatory Behavior," J. Electrochem. Soc., 132, p. 2872, 1985.
11. S. Mayer, et al., to be published.
12. S. Mayer, R. Contolini, A. Bernhardt, "Method and Apparatus for Spatially Uniform Electropolishing and Electrolytic Etching," US Patent #5,096,550, 1992.
ROBERT CONTOLINI received his PhD degree in physical chemistry from Ohio State University in 1981. In 1996, he became a senior technologist at Novellus Systems, involved with copper CVD processing. In 1987, he joined the Microelectronics Program at LLNL, where his research included electrodeposition and electropolishing. He has published 21 journal articles and is co-author of seven patents.
STEVE MAYER received his PhD degree in 1989 from U.C. Berkeley, where he studied electrochemical interfaces. In 1993, he co-founded PolyStor Corp., where he is director of research.
TIM GRAFF is senior mechanical technologist in the Electrochemical Technology Group at LLNL. Currently, his projects include electrodeposition for ULSI applications and development of new processes for flat panel displays.
LISA TARTE is a senior technician in the Microelectronics Division of the Electrical Engineering Department at LLNL. In 1986, she joined LLNL, where she became involved in all aspects of electronic packaging. She is co-author of a patent on an etching technique.
ANTHONY F. BERNHARDT received his PhD degree in 1975 from the University of California at Davis. He is program leader for microelectronics at LLNL and director of its Center for Microelectronics and Optoelectronics. Lawrence Livermore National Laboratory, PO Box 808, Livermore, CA 94550; ph 510/423-7801, fax 510/422-7309.