A new way to make SOI wafers

05/01/1997

A new way to make SOI wafers

Paul K. Chu, City University of Hong Kong, Kowloon, Hong Kong

Xiang Lu, S.S.K. Iyer, Nathan W. Cheung, University of California, Berkeley, California

Silicon-on-insulator (SOI) is generally regarded as a better substrate material than bulk silicon for deep submicron ULSI devices. Wider usage has been hampered by high production costs, however, and the expected introduction of 300-mm wafers will exacerbate the situation. Plasma immersion ion implantation (PIII) provides a viable alternative for the fabrication of SOI wafers as the processing time is very short and independent of wafer size. Two types of SOI materials, separation by plasma implantation of oxygen (SPIMOX) and bonded SOI, have been produced by PIII. This article discusses the synthesis of SOI wafers by PIII and some of the obstacles that must be overcome before the technique can become a commercial process.

SOI offers many inherent benefits over bulk silicon substrates for high speed, low-power complementary metal oxide semiconductor (CMOS) integrated circuits. Advantages include low parasitic capacitance, radiation hardness, high packing density, absence of latch-up, and compatible fabrication processes [1-3]. As the design rule of IC fabrication drops below 0.18 mm, short channel effects, source/drain punch-through, and hot carrier-induced reliability problems become more pronounced for devices fabricated in silicon substrates [4, 5]. Hence, SOI appears to be the preferred substrate material for ULSI technology.

Two methods are commonly used to fabricate SOI materials in silicon, namely separation by implantation of oxygen (SIMOX) and wafer bonding/back-etched SOI (BESOI). Both methods produce commercial quality but expensive wafers. In the SIMOX process, a high dose of oxygen, ranging from the low 1017 atoms/cm2 for thin SIMOX wafers to over 1018 atoms/cm2 for thick SIMOX wafers, is implanted into a silicon wafer at an elevated temperature. Due to the long implantation time, the cost of SIMOX wafers is much higher than that of silicon substrates.

In wafer bonding/BESOI, two wafers (at least one oxidized) are pasted together using wafer bonding techniques, and one side of the bonded wafer is polished until the desired silicon film thickness is obtained. This process allows much easier and independent adjustment of the buried oxide and silicon overlayer thicknesses. SOI wafers fabricated by the wafer bonding process are more expensive than bulk silicon wafers because two wafers are needed to produce a single SOI wafer, and the polishing process can be quite expensive. As 300-mm wafers are projected to be the substrate of choice in the future, the high cost of SOI wafers prepared by these two conventional methods will be a bigger factor and could directly impact the profitability of IC companies.

Figure 1. Schematic of the PIII process.

Plasma immersion ion implantation

PIII has created a great deal of interest in the microelectronics field [6, 7]. For example, it has been applied to form shallow junctions, passivate flat panel display materials, and dope trenches [8-11]. In PIII, the sample is immersed in a plasma shroud from which ions are extracted and accelerated through a high voltage sheath into the wafer (Fig. 1). Because of the absence of beam filtering and collimation optics, a PIII reactor can attain a dose rate as high as 1016 ions/cm2sec, which is equivalent to 10 monolayers of implanted atoms/sec and at least an order of magnitude higher than that of a conventional ion implanter. Since the entire sample is implanted simultaneously, the implantation time is independent of sample size. Figure 2 compares the time required to implant a dose of 1 ? 1018 atoms/cm2 of oxygen, and shows that the significant time saving using PIII increases with larger wafers.

Figure 2. Comparison of the implantation time for a dose of 1 ? 1018 atoms/cm2 by PIII (1 mA/cm2) and a high current beamline ion implanter with an ion current of 60 mA.

Figure 3. SPIMOX annealing process.

PIII is now being used to synthesize SOI wafers. The first attempt was directed to the formation of thin SIMOX wafers using an oxygen plasma [12-14], the SPIMOX fabrication process. In order to obtain a continuous layer of buried oxide, several precautions must be taken. First, the substrate temperature must be kept at 6008C or higher during PIII in order to minimize implantation-induced damage and facilitate the subsequent annealing
ipening process. No sample heating is necessary, however, because the sample is heated significantly by the high ion flux, and the substrate can be kept above 6008C by proper adjustment of the implantation conditions. The post-PIII thermal treatment directly impacts the quality of the materials and must be done at 13008C for a period of two to six hours in an oxygen-free environment (Fig. 3).

The energy required to implant oxygen into the wafer is typically higher than 50 kV, and the oxygen pressure in the plasma must be lower than 10-3 torr in order to prevent gas breakdown. Enough oxygen ions must be implanted to give a local oxygen-to-silicon ratio of 2:1, to ensure stoichiometric formation of SiO2. Rutherford backscattering spectrometry (RBS) of the oxygen concentration depth profile correlates with XTEM micrographs showing scattered oxide precipitates when the dose is too low (for example, 1 ? 1017 atoms/cm2).

Another interesting phenomenon that manifests in the RBS depth profile is that the oxygen depth distribution is quite spread out. The oxygen profile is a superposition of two peaks, the first one arising from implanted O2+ (25 kV net energy) and the second peak stemming from O+ (50 kV net implantation energy). Thus, in order to form a continuous buried oxide, the in-depth distribution (straggle) of oxygen must be narrowed and the implantation dose must be raised. The first requirement can be satisfied by adjusting the plasma parameters preferentially to favor O2+. Secondary ion mass spectrometry (SIMS) has shown that under optimized conditions, the implanted O2+ flux can be higher than that of O+ by more than 10 times.

With O2+ as the dominant species and the oxygen dose high enough, the Oswald ripening process will deplete oxygen from both sides of the O2+ peak to form one single oxide layer. The total time to implant the necessary dose of 3 ? 1017 atoms/cm2 is less than five minutes. The interfaces may exhibit a small degree of waviness that can be minimized by annealing at a higher temperature. The quality of the top silicon layer can also be improved by using a higher implantation energy and higher annealing temperature [15]. Optical measurements indicate that the lateral homogeneity of current SPIMOX wafers is not as good as that of commercial SIMOX wafers prepared by conventional beamline ion implantation.

To further reduce the implanted oxygen profile straggle, a water plasma can be used as an alternative source [15]. Though there are three dominant species in a water plasma, H2O+, HO+, and O+ (Fig. 4), the masses of these three species are very close. The resulting implant has a very tight distribution, as shown in Fig. 5. The thicknesses of the overlying silicon and oxide layers are 20 nm and 70 nm, respectively. The silicon layer obtained is polycrystalline because the wafer temperature during implantation is below 4508C. Crystallinity can be improved by implanting at a higher temperature (>6008C) and annealing at a higher temperature and for a longer time.

PIII SIMOX limitations

Even though the experimental results strongly suggest that PIII is feasible for fabrication of SIMOX materials, the process needs to be refined before it can be commercially viable. Since there are no filtering and collimating elements in a PIII reactor, contaminants in the plasma are co-implanted. Most of these impurities are expected to be trapped in the oxide or at the oxide/silicon interfaces during the Oswald ripening process and thus depleted from the active silicon overlayer. Nonetheless, real devices must be fabricated in SPIMOX wafers to check carrier lifetime and electrical behavior.

Figure 4. The convoluted oxygen distribution as a superposition of three implants due to H2O+, OH+, and O+. Since the three implantation ranges are quite close, the resulting peak is quite sharp, as compared to an oxygen plasma.

Figure 5. XTEM of the SPIMOX wafer formed using a water plasma.

The lack of temperature control on the PIII sample stage can be a concern in a commercial environment where high throughput is desired. Either over-heating (leading to wafer melting in the extreme case) or under-heating (causing incomplete recrystallization and extensive defects in the silicon overlayer) can be deleterious. The implementation of sample heating and cooling is not trivial in PIII because the sample is subjected to a high voltage, and new sample stages with efficient heating and cooling mechanisms must be designed.

Post-implantation thermal treatment typically requires a long annealing time (2-6 hours) at a temperature over 13008C. The ambient in the furnace must be oxygen-free, otherwise inadvertent oxidation can easily consume the thin overlying silicon layer even when a nitride capping layer is used.

Last but not least, uniformity must be addressed. Even though novel plasma sources exist that are capable of yielding very uniform plasma density (better than ? 2% across a 300-mm wafer), it remains to be seen whether they can achieve these uniformities with oxygen and water plasmas.

The bond-cut process

Recently, a bond-cut process (the "Smart-Cut" process developed by SOITEC) has yielded excellent SOI wafers [16]. This process has injected new life into the wafer bonding/BESOI technology because one of the bonded wafers can be recycled, and so only one silicon wafer is consumed in the formation of a SOI wafer (Fig. 6). The first critical step is to implant a fairly high dose of hydrogen or helium into the wafer to form a plane along which the bonded wafer can be cracked. Implantation of a high enough dose of helium creates cavities, and cracking can take place along this plane after 10508C annealing for 30 minutes [17].

Figure 7. TEM picture of Si/oxide/Si3N4/oxide/Si structure synthesized using helium PIII and bond-cut. The top silicon wafer was implanted using a helium plasma at 33 kV with a dose of 1 ? 1017 atoms/cm2. The bonded interface is between the top oxide and nitride layers.

Figure 6. Schematic of the bond-cut process.

PIII is attractive for this step because the implantation time is independent of the wafer size. Figure 7 shows the XTEM picture of an SOI test structure formed by the bond-cut process in conjunction with plasma immersion ion implantation [18]. Helium PIII (1 ? 1017 cm-2 dose) at 33 kV is first carried out. The implanted wafer is then bathed in a high-pH solution and hydrophilically bonded with an oxide/nitride coated substrate at room temperature. The implanted wafer cracks along the implanted helium peak region by annealing at 5008C, and the SOI structure is finally annealed at 11008C for 60 minutes to solidify the bonding. Similar results can be achieved using hydrogen plasma immersion ion implantation.

PIII bond-cut limitations

When compared to SPIMOX, the PIII/bond-cut requirements are quite different. For example, unintentional contamination and ion flux uniformity may not be as critical since the cracked surfaces will be polished away by chemical mechanical polishing. The implantation energy must be high in order to implant hydrogen or helium deep into the wafer. Because of the relatively shallow penetration depth of He when compared to hydrogen, the 100 kV upper limit on most PIII equipment may render helium PIII/bond-cut impractical.

For hydrogen PIII/bond-cut, the presence of H+, H2+, and H3+ in the plasma tends to spread the implanted hydrogen profile so much that cracking may not occur uniformly. Consequently, the PIII operating conditions must be refined to favor one of the three species. If the projected range is the primary factor, H+ will be preferable because it will have the highest penetration depth of the three species. However, H3+ forms fewer defects due to its lower impact energy. More studies will be necessary to determine the best species and optimal implantation conditions.

Another concern is the implantation temperature. Unlike SPIMOX, the desired PIII temperature for bond-cut is below 2508C, so that a substantial amount of the implanted hydrogen can be retained. All these difficulties can, in principle, be overcome by manipulating the plasma parameters and designing a sample cooling mechanism.

Conclusion

In sum, both the SPIMOX and PIII/bond-cut approaches are very promising. If the technical difficulties inherent to the processes can be overcome, PIII may one day replace conventional ion implantation in the production of commercial SOI materials. n

Acknowledgment

Smart-Cut is a trademark of SOITEC.

References

1. H. Vogt, et al., Solid State Technology, 34 (2), p. 79, 1991.

2. J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publisher, Boston, MA, 1991.

3. P. N. Dunn, Solid State Technology, 36 (10), p. 32, 1993.

4. T. Tsuchiya, T. Ohno, Y. Kado, in S. Cristoloveanu (Ed.), Silicon-on-Insulator Technology and Devices, Electrochemical Society, Pennington, NJ, p. 401, 1994.

5. Y. H. Cheng, Y.Y. Wang, Int. Workshop on VLSI Process and Device Modeling, Japan, p. 102, 1991.

6. J. R. Conrad, J. L. Radtke, R. A. Dodd, F. J. Worzala, N. C. Tran, J. Appl. Phys., 62, p. 4591, 1987.

7. J. V. Mantese, I. G. Brown, N. W. Cheung, G. A. Collins, MRS Bulletin, 21 (8), p. 52, 1996.

8. B. Mizuno, et al., Surf. Coat. Technol., 85, p. 51, 1996.

9. S. Qin, J. D. Bernstein, C. Chan, J. Zhao, S. Denholm, Surf. Coat. Technol., 85, p. 56, 1996.

10. P. K. Chu, C. Chan, N. W. Cheung, Semiconductor Int., 6, p. 165, 1996.

11. P. K. Chu, et al., to be published in Mat. Sci. & Eng.: Reports.

12. J. Min, et al., Mat. Chem & Phys., 40, p. 219, 1995.

13. J. B. Liu, et al., Appl. Phys. Lett., 67 (16), p. 2361, 1995.

14. J. Min, et al., Surf. Coat. Technol., 85, p. 60, 1996.

15. J. B. Liu, et al., Proc. IEEE Int. SOI Conf., p. 166, 1995.

16. M. M. Bruel et al., Proc. IEEE Int. SOI Conf., p. 178, 1995.

17. J. Min, et al., to be published in Thin Solid Films.

18. X. Lu, et al., Proc. IEEE Int. SOI Conf., p. 48, 1996.

PAUL K. CHU received his BS degree in mathematics from Ohio State University and his MS and PhD degrees in chemistry from Cornell University. He is currently a professor in the Dept. of Physics and Materials Science at the City University of Hong Kong, advisory professor in the Institute of Materials Science at Fudan University, China, and joint professor in the Dept. of Computer Science of Beijing University. Dept. of Physics and Materials Science, City University of Hong Kong; fax 852/2788-9549 or 7830, e-mail [email protected].

XIANG LU received his BS degree in applied physics at Tsinghua University, Beijing, China, and his MS degree in materials science and mineral engineering from the University of California, Berkeley, where he is a PhD student researching IC processing, ion-beam and plasma processing technology, and SOI materials and technology.

S. SUNDAR KUMAR IYER received his B. Tech and MS degrees in electrical engineering at the Indian Institute of Technology, Madras. Currently, he is working on SIMOX fabrication with plasma immersion ion implantation for his doctoral degree at the University of California, Berkeley.

NATHAN W. CHEUNG is a professor in the Dept. of Electrical Engineering and Computer Sciences at the University of California, Berkeley. His research activities include ion-beam and plasma processing technologies, VLSI metallization, IC processing and reliability, and high bandgap semiconductors.