Japanese manufacturers still working on CMP processes

05/01/1997

Japanese manufacturers still working on CMP processes

A new report on the use of chemical mechanical planarization found only four out of Japan`s top 10 semiconductor manufacturers using the high-profile process in their facilities. Of the six other firms surveyed, five are evaluating CMP in pilot phases or development lines; one company is still in the research stage. In the report, "Survey on CMP Utilization in Japanese Volume Production Lines and Their Future Plans," the majority of manufacturers said several issues related to CMP use still need fine-tuning, including pattern dependency, wafer cleaning, and polishing reproducibility. Despite those issues, the survey participants did find good reason to employ the CMP process, a business that grew 20% last year, and is expected to be a $900 million business in 2001, according to market researcher Dataquest.

All 10 companies ranked the benefits of planarization as the top incentive for using CMP. Some firms offered other reasons, such as better cost of ownership, higher yield and throughput, and fewer process steps. The majority of companies said they prefer having CMP systems installed in the same cleanrooms with other equipment; however, some of those manufacturers said they have separate air circulation systems in the cleanroom or isolate CMP equipment with walls within the cleanroom.

All companies chose CMP for use on logic ICs, but many said they would use the process on DRAMs and SRAMs. The companies said CMP is being used on TEOS film, and most said CMP is being used on tungsten, BPSG, copper, polysilicon, and aluminum.

While manufacturers could agree on these questions of CMP use, few shared the same expectations of equipment and the CMP process itself. For example, while one manufacturer said it expected a throughput of 20 wafers/hr, another demanded 100/hr. The same applied to polishing speed: two manufacturers were content with 250 nm/min, but another two wanted at least 500 nm/min. Six manufacturers said they expected a 3% uniformity between lots; the remaining were split between 5 and 10%. For uniformity within a single wafer, four manufacturers expected at least 3%; another four said 5% would do.

The report, published by Science Forum, is available only in Japanese. For more details, contact Takeshi Hattori, editor; fax 81-46-230-5572, [email protected]. - Christine Lunday, WaferNews