SPIE: Optical lithography pushes the limits

05/01/1997

SPIE:Optical lithography pushes the limits

More than 2000 engineers, scientists, and executives attended the 1997 SPIE Lithography Symposium, dramatically more than last year. When the semiconductor industry is making a technology transition, business looks bad, but the leading-edge technology meetings expand. That seems to be the case in 1997 as the transition to 250 nm with DUV lithography has accelerated. Gates on nominal 250-nm chips are being shrunk to 200 nm in search of greater speed, but that creates a challenge for process control.

The acceleration in DUV acceptance caught most of the industry by surprise. Nikon expects to ship more than 200 DUV units in 1997, according to John Wiesner, Senior VP engineering. Cymer, the dominant supplier of KrF excimer lasers for lithography, has expanded from 42 people to 410, according to Robert P. Akins, president and CEO. They had 66 job postings at the SPIE Symposium and plan to ration the 400 or so lasers produced in 1997. Both ASML and Canon also have scanner systems capable of sub-250-nm resolution over extended fields.

A panel discussion moderated by Wil Conley of IBM discussed options for reflection control in the DUV era, which is essential for gate width uniformity. John Sturtevant of Motorola stated the problem: to keep gate width variation below 1%, the reflected light level has to be <0.5%. Each nanometer of gate width variation costs 1 MHz in chip speed and $7.50/chip in selling price. The standard TiN ARC changes the dissolution dynamics of chemically amplified resists, creating "feet" in positive resist patterns and undercutting negative resists. Thus the industry is investigating a variety of organic and inorganic ARC layers. The organic materials tend to be thick and planarizing, making gate width control difficult simply through geometery. The new inorganic materials such as SiOxNy are thinner and conformal, but difficult to remove. Some claim that this ARC layer can be left in the chip. PECVD methods allow inorganic ARCs deposited using Novellus and Applied Materials tools to be tuned to minimize reflectivity. (see "Dielectric antireflective coatings for DUV lithography," Bencher, et al., March, p. 109). Depending on the process, one or another type of ARC may be better than the others. With many materials but no consensus, SiOxNy looks likely for gates (left on the chip), and new organics for everything else.

The Lithography Working Group of the SPIE held a discussion chaired by Mircea Dusa of National Semiconductor on "Optical Lithography at the Resolution Limit - How Far Can We Push It?" The consensus was that it could be pushed to 130 nm and below. Tim Brunner of IBM predicted 80-nm circuits within 10 years. However, Fabian Pease of Stanford and DARPA reported that "SEMATECH is panicking" and looking at interferometric and nonoptical methods such as hot-pressing. According to Pease, any post-optical system must work at 50 nm, at which point the 25 W/?m interconnect resistance dominates. Hiroshi Ohtsuka of ASET presented some 110-nm line-space patterns made on a single layer resist with alternating PSM at 193-nm and some 90-nm patterns made with a TSI resist.

Steve Brueck of the University of New Mexico described a 300-mm interferometric lithography tool delivered to SEMATECH by Interserv of Bloomington, MN. This device is intended to make 300-mm diameter wafers with a selection of regular resist patterns for testing processing equipment. The initial results indicate that 180-nm 1:1 line-space patterns can be made in 600-nm thick resist, and corresponding contact patterns can be opened, but with some resist loss. However, this machine uses i-line resist, which may have different processing properties than the DUV resists used on chips.

John Nistler of AMD described the first production of ULSI chips using alternating phase-shift mask technology. By shrinking gates and making them more uniform, AMD was able to raise the speed and increase yield by about eight more good chips/wafer for one of their key products. Paul Ackmann of AMD described how the exposure of chips in different locations around the wafer could be changed (by "practically perfect patterning people") to account for etch variations. This "exposure compensation" worked best with AA-PSM masks at i-line. In a keynote talk at the Metrology Conference, Bill Arnold of AMD advocated using electrical tests for linewidth measurements, avoiding problems arising because low-voltage SEMs are 1 generation behind the SIA roadmap. At the gate level, CD variations must now be held to below 8%, according to Arnold, not the 10% contemplated in previous roadmaps. - M.D.L.