Issue



X-ray masks report progress at SPIE


05/01/1997







SPIE Microlithography report

X-ray masks reportprogress at SPIE

X-ray lithography (XRL) researchers are currently battling for the hearts and minds of lithographers developing =0.18-?m processes. Approximately 40 people attended an invitation-only seminar sponsored by Suss Advanced Lithography (SAL) on x-ray mask making during the 22nd annual SPIE International Symposium on Microlithography in Santa Clara, CA.

Masks have long been the biggest challenge to developing a production-worthy XRL infrastructure. US researchers, led by IBM, had been working with boron-doped silicon substrates with gold lines, while the Japanese had settled on tantalum (Ta) lines on silicon carbide (SiC) substrates.

The IBM/Motorola/Lockheed-Martin/DARPA consortium produced its last 1-Gbit DRAM R&D masks using the silicon/gold technology, and will now work exclusively with SiC/Ta. Tantalum can be brushed and chemically cleaned, making it easier than gold to work with. SiC also has a higher biaxial elastic modulus (530 for SiC vs. 180 GPa for B-Si) that results in a stiffer membrane and lower image placement error. Mask bow should be approximately 10-?m convex.

X-ray mask duplication is possible, and the Center for X-ray Lithography (CXrL) presented a paper at the main conference. However, both IBM and Motorola are uncomfortable with the potential for duplication errors and plan to use direct write e-beam exclusively.

A global XRL infrastructure is beginning to emerge. Since the challenges of alignment and stepping are the same or possibly simpler compared to optical lithography, there`s no reason why Canon or Nikon can`t jump in and produce an x-ray stepper if a market rapidly emerges. SAL`s x-ray steppers use an efficient scanning system to raster the beam on a stationary mask-wafer assembly; the beam is 2-3-mm wide and 50-mm long. Overlay accuracy of x-ray steppers with mask error removed is currently 40 nm. Peter Heinz, SAL`s CEO, stated that system improvements should improve overlay to 25 nm.

One significant difference between XRL and optical litho is the illumination source. X-ray point sources have been under development for many years, but success has not yet occurred. Without point-sources, XRL relies on $15-20 million synchrotrons for illumination.

Oxford Instruments` synchrotron occupies 6 ? 2 m of cleanroom space, with up to 20 two-m long beamlines. Oxford claims better than 98% uptime, which would certainly be minimal for a sub-component that could simultaneously take down all critical layer steppers in a fab.

An excerpt from a SEMATECH report summarizing the major challenges to 0.13-?m XRL was presented as a starting point for discussion. The major issues raised include:

 refractory mask manufacturing demonstration,

 commercial supplier for mask writer (commitment with schedule),

 convincing demonstration of mask stability, and

 stepper magnification correction demonstration (proof of concept with data).

Franco Cerrina, director of the CXrL at the University of Wisconsin, responded to the first three of the SEMATECH issues:

 With IBM`s switch to tantalum, a clear path has been defined.

 Leica makes a field emission tip e-beam writing tool with 18 nm 3s accuracy, but it`s relatively slow. The system`s 40 MHz internal clock speed currently takes approximately 12 hours to produce a single 1-Gbit DRAM mask. Clock speed increasing four-fold would be desirable.

 Radiation stability should not be a significant problem for SiC. Experiments were conducted to simulate mask exposure levels for high-volume production, based on the following estimates: 40,000 wafers/mask, 50 fields/wafer, and 100 mJ/cm2 resist. Based on these estimates, experiments were conducted with 100 kJ exposures, and results were reasonable. Faster resists under development should lessen any potential problems.

The fourth issue was addressed by software developed by IBM`s Mask Shop. R. Jagannathan, manager of x-ray mask development at IBM Advanced Mask Facility in Essex Junction, VT, reported that the company`s mask fabrication operation is officially open for business. Lead times are around three months until the conversion to the new SiC/Ta process is complete after the summer. The facility`s e-beam mask writer is a custom IBM design with a variable shaped beam. Mask inspection is accomplished with a KLA SEMspec system with 90-nm resolution, and repair is by a Micrion FIB system.

XRL mask fabrication starts with a 100-mm Si wafer with 2-?m of SiC deposited by Hoya Corp. (SiC deposition is critical, and IBM worked with Hoya to establish a reliable process). Deposition of 500 nm of TaSiN for the absorber is followed by 200 nm of SiON for the hard mask. Potassium hydroxide (KOH) in a single wafer system bulk etch the silicon wafer to form the membrane. TaSiN patterning is achieved with an ECR plasma etch using SNR and UV3 resist.

One inevitable problem with XRL is image expansion due to the reflection of secondary electrons in dense pattern arrays, so called, "electron-fogging." IBM`s writer uses an iterative software algorithm called "product specific emulation (PSE)" to compensate for individual mask write errors such as those caused by electron-fogging.

With the PSE iterative process, routine image placement accuracy is 40-50 nm; without it, electron-fogging increases the error to 90 nm placement accuracy. Since PSE adds time and cost to mask fabrication, a production goal is to understand and control the problems that the iterative process compensates for and thus eliminate it. Current minimum CD is 175-260 nm, with CD 3 s of 25 nm. Typical nonrepairable (such as clear) defect levels are 10-30/cm2.

Paul Castrucci, of Paul Castrucci and Associates, argued for early adoption of XRL. Transistor gate length (L) variation arises from the mask, pattern transfer to the resist, and the etch. Since XRL causes less variation in image transfer, the Lnominal of XRL is 0.170 vs. 0.173 ?m for optical lithography. The resulting tighter distribution of gate lengths thus allows a fab to produce more top-binning chips and much greater profits. Castrucci suggested that companies begin using XRL to produce some small percentage of critical layers on 0.35- or 0.25-?m products today to realize this direct benefit to the bottom line.- E.K.