Future trends in CMP

05/01/1997

Future trends in CMP

Sanjeev Chitre, Integrated Process Equipment Corp., San Jose, California

CMP has just begun to gain worldwide acceptance as an enabling process in semiconductor fabrication. Even though companies such as Intel, IBM, Motorola, and Siemens have employed CMP for the past few years, the process is still generally perceived as more art than science. In addition, there may be more near-term hurdles to widespread implementation: it is considered a "dirty" process, and the cost of the process is believed to be high.

As CMP evolves toward a truly revolutionary technology for semiconductor manufacturers in the year 2000, we will overcome these hurdles. Cleaners are presently being integrated with polishers to provide a dry-wafer-out technology. Its own contained environment, this integrated tool can be placed next to the CVD machine in a cleanroom. This area then becomes a CMP bay. The perception of the process as "dirty" is largely derived from the dirty nature of slurries.

With regard to cost, it was difficult to justify CMP as an alternative process when CMP tools had lower throughput. Under that limitation, it was reasonable to use CMP on only the high-end, high-margin products such as microprocessors and ASICs. Now that we have high-throughput tools, the process can compete on more types of devices and more layers of interconnect. From the customer`s point of view, total cost of ownership for CMP includes the equipment and all the consumables, primarily DI water and slurries. With recycled water and reprocessed slurries, lower cost of ownership can now become a driving force for competitive technology replacement, even in the memory business. The cost of ownership advantage of reprocessed slurries is heightened when dealing with metals, since the original slurries are two to three times as expensive as those for oxides.

Once semiconductor manufacturing moves to 256 Mbit and on to 1 Gbit of memory, as is currently occurring, close tolerances will be required of the CMP process. For present and next-generation devices, specifications limited by the flatness of the wafer are reasonable and are being met satisfactorily by the CMP process. But, in the future, with <0.15-?m geometries, more critical tolerances will be needed. CMP can deliver these specifications as it integrates science - in the form of measurement - into the process.

It will be necessary to measure thousands of points across the wafer-instantaneously. This will involve endpoint detection, in situ metrology, pre-CMP process measurement, and post-CMP measurement. The specifications for local, as well as global, planarization will help ensure consistent results chip-to-chip and across the wafer. Yield improvement will drive the worldwide adoption of CMP.

On a commercial scale, the future can bring CMP technology that is delivered as a toll charge: a cost/wafer processed and delivered. The elements are in place. The next generation of CMP tools will produce ultraflat wafers, using both macro- and micro-planarization. Our technology in the year 2000 may be a combination of CMP and plasma or laser technology: true adaptive planarization.n

SANJEEV CHITRE is the chairman of the board and CEO of Integrated Process Equipment Corp., 911 Bern Court, San Jose, CA 95112; ph 408/436-2170; fax 408/436-2179.