Low-temperature polysilicon reshapes FPD production
05/01/1997
FIRST OF TWO PARTS
Low-temperature polysilicon reshapes FPD production
Julian G. Blake, Michael C. King, James D. Stevens III, Eaton Flat Panel Equipment, Beverly, Massachusetts
Ross Young, DisplaySearch, Austin, Texas
Many liquid crystal display (LCD) manufacturers are directing considerable effort toward the development of low-temperature polysilicon (LTPS) technology, because it promises to produce higher-performance displays at lower cost. The success of LTPS depends on new device structures, new processes, and process equipment designed specifically for this technology. This article addresses critical processes that will require development.
LCD manufacturers are constantly challenged to produce higher-performance displays at lower cost. In the 1980s, market demand forced a transition from passive twisted nematic (TN) displays to passive supertwisted nematic (STN) displays, and then to today`s amorphous silicon and LTPS active-matrix liquid crystal displays (AMLCDs). LTPS technology has drawn the attention of many display manufacturers because it has several potential advantages over amorphous and high-temperature polysilicon.
Compared to amorphous silicon, polysilicon has higher electron and hole mobilities. Device design rules can shrink; self-alignment features are possible; and pixel-charging time decreases, facilitating higher gray scale, color, and real-time video. Pixel aperture ratios become larger, producing brighter and lower power displays. The smaller size and improved performance of polysilicon thin-film transistors (TFTs) also make them suitable for higher-definition display applications.
Moreover, better TFT performance may be coupled with lower panel-manufacturing costs. Driver circuitry, which typically accounts for 5-30% of the total panel cost, can be integrated into a polysilicon display. Fabricating the drivers directly on the glass eliminates the traditional tape-automated-bonding driver package, simplifies the display module process, and slashes module process equipment costs. Integration not only reduces costs, but increases reliability and module process throughput because fewer interconnects are needed. In addition, the large reductions in pixel-charging time allow "point-at-a-time" addressing architectures, which dramatically reduce the number of required driver circuits. The panel controller, memory, and other circuitry could also be integrated onto the panel once a mature LTPS production process is established. Polysilicon SRAMs and high-voltage circuitry lend themselves to a wide range of integrated "system-on-glass" applications.
Conventional high-temperature polysilicon processing requires quartz substrates (up to 200 mm2) that are too expensive except for very small display sizes (typically <1.5 in. dia.). LTPS technology uses less expensive standard glass substrates (up to 550 ? 650 mm).
LTPS will clearly have a market in small- and medium-sized (2 to 8-in.) high-resolution displays, as amorphous silicon will probably not be able to match the resolution, power consumption, and lower cost. Sanyo and Sony have already introduced LTPS displays into this market. Extension of LTPS to larger displays, such as the 10 to 20-in. panels demanded by the notebook PC and CRT monitor replacement markets, will depend on whether the costs of additional process steps and specialized processing outweigh the cost reductions from integrating the driver circuitry. On the other hand, high-performance LTPS panels may be able to command a price premium.
DisplaySearch recently completed a detailed technical and cost study comparing LTPS vs. amorphous silicon display technology [1]. A Monte Carlo model developed at Stanford University was updated with data from LTPS producers and suppliers [2]. Three different panel sizes (3 in., 6 in., and 12 in.) with XGA resolution were examined. The study assumed second-generation fabs using 360 ? 465 mm substrates with a 20% increase in equipment costs for the LTPS fab to achieve the same throughput. Seventy-five percent effective yields were assumed for both technologies.
LTPS technology will not initially achieve the same yields as amorphous silicon due to the additional masks, added process steps, and integrated driver circuitry. Therefore, the study calculated the LTPS yields required to achieve an equivalent cost, modelling two different LTPS driver-integration scenarios. In the first scenario (A), the row circuitry was fully integrated, but only switches and shift registers were integrated in the column circuitry. A single external driver IC, including the multiplexed digital-to-analog converter and amplifiers, was mounted off panel. The second scenario (B) fully integrated all of the required driver circuitry on the panel as well as the panel ASIC (Fig. 1).
Figure 1. Cost analysis of low-temperature polysilicon vs. amorphous silicon TFT-LCDs; a) gives the cost of each panel size in each scenario, and b) gives the yield required for scenarios A and B to be cost effective. Scenario A assumes partial driver integration; scenario B assumes full integration.
Whether or not LTPS will be able to achieve these lower costs at the larger panel sizes will depend on process and tool development. Part 1 of this article discusses polysilicon device structures and crystallization of amorphous silicon. Part 2 will discuss lithography, implantation, and other technologies needed for process integration of LTPS.
LTPS TFT structures
Today`s amorphous silicon TFTs are typically bottom-gate, "partially self-aligned" NMOS devices (Fig. 2). The first layer above the glass substrate is the 300-nm thick MoTa alloy gate metal, with gate dielectric layers of 300-nm SiO2 and 230-nm SiNx directly above. A 100-nm amorphous silicon channel, deposited above the gate dielectric, is passivated by a 300-nm SiNx layer. A 50-nm n+ amorphous silicon layer provides source/drain contacts for the 500-nm aluminum source/drain and address/data line interconnect layer. A 200-nm transparent indium tin oxide (ITO) conductor above the aluminum layer forms the liquid crystal cell electrode. The topmost layer, 300 nm of SiNx passivation, seals the device against environmental degradation.
Figure 2. Cross section of a typical amorphous silicon TFT.
This process is partially self-aligned because the gate metal pattern defines the channel protection layer, which helps to align the source/drain regions of the TFT with the channel. These devices require 3-7 masking layers. Amorphous silicon TFTs typically have mobilities of just 0.5 cm2/V-sec, leakage currents <1 pA, and threshold voltages of 3 V. All of the amorphous silicon process steps are mature, with three generations of manufacturing equipment developed and implemented in mass production.
LTPS TFTs can be fabricated with either bottom- or top-gate NMOS processes. The driver circuitry, however, is fabricated by top-gate CMOS. Figure 3 shows a top-gate LTPS pixel TFT. First, a layer of CVD amorphous silicon is converted to polysilicon. CVD SiO2 and plasma CVD SiNx, deposited over the outlined transistor, form the gate dielectric layers. The metal gate is deposited and etched. Next, the phosphorus source/drain implants use the gate pattern as a mask. Either extended annealing in hydrogen or an excimer laser activates the implant. Sputtered aluminum, deposited in vias etched through the gate, forms source/drain contacts and serves as the data/address lines. Transparent ITO is sputtered on to form the electrode area. The device receives a final SiNx passivation layer. This process is "fully self-aligned" because the gate serves directly as the source/drain implant mask. LTPS devices typically have mobilities of 50-100 cm2/V-sec, leakage currents of 1-10 pA, and n-channel threshold voltages of 1-2 V. Figure 4 compares process flows for amorphous silicon and LTPS TFTs. Integrated on-glass CMOS driver circuits require a more complicated process flow with added ion implant and photolithography steps.
Figure 3. Cross section of a typical LTPS TFT.
Figure 4. Process comparison: a) amorphous silicon TFT vs. b) LTPS TFT.
LTPS devices typically use 6-9 masks. Some of the additional steps accommodate the driver circuits by doping the driver source and drain regions. The remaining steps create a lightly doped drain or offset to reduce the inherently high leakage current of LTPS.
Bottom-gate polysilicon structures are more compatible with amorphous silicon processes because the process flow is quite similar. One manufacturer has even eliminated the ion implantation or shower requirement by simultaneously crystallizing and activating n+(p+) a-Si:H deposited by plasma-enhanced chemical vapor deposition (PECVD) [3]. Resistivity suffered, however, and top-gate TFTs offer better performance. The top-gate design process is more similar to semiconductor than display manufacturing. It can be manufactured at higher temperatures; and achieves lower leakage currents, higher mobilities, and higher-quality devices than bottom gate. The bottom-gate approach, therefore, only benefits manufacturers who aim to convert their amorphous silicon lines to LTPS at low cost.
LTPS technology has been in the R&D lab for nearly 10 years, but is now making its way to the production floor. Several major suppliers have developed or announced specialized LTPS equipment in the last 12 months. Most of this equipment is now available for 550 ? 650 mm and larger substrates.
LTPS manufacturing challenges
LTPS must overcome a number of significant production challenges to realize these benefits. Typically, all processing must be conducted at 450?C or lower in order to use low-cost glass substrates. The LTPS process also differs from the amorphous silicon process in several significant respects. Reduced hydrogen content amorphous silicon CVD, annealing equipment, ion implantation doping equipment, a new gate dielectric CVD process, finer resolution lithography equipment, and hydrogenation equipment will all have to be introduced.
Amorphous silicon deposition. LTPS developers have so far elected to deposit amorphous silicon and then crystallize it to form polysilicon. Competing approaches include direct polysilicon deposition with LPCVD and SiH4 or Si2H6, direct amorphous silicon/polysilicon deposition, solid-phase crystallization, hydrogen radical-enhanced CVD using SiF4 and H2, and catalytic CVD [4-6]. All of these approaches suffer from temperature, mobility, uniformity, or throughput limitations relative to amorphous silicon deposition and crystallization. Deposition in the amorphous silicon phase also gives a smoother interface at the gate dielectric as there is no crystallographically preferred growth direction. This smoother interface improves device performance and reliability.
Amorphous silicon deposition for LTPS displays differs from that for amorphous silicon displays because the hydrogen concentration must be less than 3%. At higher hydrogen concentrations, the laser-annealing process will cause sudden desorption of hydrogen, resulting in a rough surface or ablation. If the hydrogen concentration after amorphous silicon deposition is higher than 3%, dehydrogenation can be performed by laser annealing or furnace annealing. Both can reduce the hydrogen concentration to under 3%, but suffer from low throughput.
LPCVD amorphous silicon deposition, typically at 450?C with Si2H6 gas, produces films with nearly no hydrogen concentration. PECVD-deposited amorphous silicon using SiH4 at 300-350?C has suffered from typical hydrogen concentrations of 15-20 wt %. However, ULVAC Technologies Inc. and AKT have both recently introduced commercial PECVD systems with acceptable hydrogen concentration. ULVAC research shows that the hydrogen concentration gradually increases as radio frequency (RF) input power increases. RF power of <1 kW gave a hydrogen concentration under 1.5%.
According to AKT`s CVD GM, Kam Law, PECVD is preferred to LPCVD because PECVD:
produces better uniformity over larger substrates and is more scaleable;
deposition rates are higher;
requires lower temperatures; and
tools have lower contamination due to in situ cleaning [7].
Film-thickness uniformity is especially critical as optimal laser-energy density varies widely with amorphous silicon film thickness [8]. After crystallization, PECVD also tends to produce larger grain sizes and therefore higher mobilities at lower laser-energy densities than LPCVD [9].
Most manufacturers already have larger substrate PECVD systems that can be converted to LTPS production. Amorphous silicon film thicknesses for LTPS (40-60 nm) are less than in amorphous silicon TFTs, and deposition times are similar (60-90 sec). Key challenges will be to continue to minimize hydrogen concentration, particulates, and process temperature, while increasing deposition rates.
Crystallization. Once the amorphous silicon has been deposited, it must be converted to polysilicon by one of three different methods - solid-phase crystallization furnace annealing, rapid thermal annealing, or excimer laser annealing. Critical parameters include grain size, mobility, uniformity, process temperature, and throughput.
In solid-phase furnace annealing, the amorphous silicon film is implanted with silicon ions and annealed for as long as 40 hr [4]. The resulting polysilicon grain size depends on the dose, implantation energy, and precursor films. Higher doses result in larger grains that reach a maximum of 1-2 ?m, but also require long annealing times at temperatures up to 600?C to repair the damage to the substrate. Field-effect mobilities over 100 cm2/V-sec for n-channel have been achieved; 25-50 cm2/V-sec is common, but process throughput is very low.
Rapid thermal annealing dramatically shortens the process time relative to furnace annealing. This method exposes a small portion of the substrate to temperatures beyond the strain point of the glass, while using the rest of the substrate as a stable back plane. Throughput is typically 60 substrates/hr.
Preheating the substrate to 500?C with infrared heaters reduces thermal shock. Then, high-energy Xenon arc lamps expose approximately 5% of the substrate to temperatures beyond the strain point of the glass. Only the silicon film absorbs the spectral radiation produced by the lamps, as glass is transparent to it [10]. Conduction heats the glass substrate to just below the film temperature, but only within a 1-cm width. So, the light beam must be uniformly focused to eliminate glass warpage due to uneven thermal distribution. By processing the glass at 750?C with lamp exposure times of 1 sec, Intevac Inc. achieved <0.15 mm in substrate warpage, with mobility results >50 cm2/V-sec and 15 pA of leakage current [11]. LTPS users often have more stringent requirements, however. In addition, as the substrate is heated above 600?C, impurities can diffuse into the silicon film and increase the leakage current, particularly at large, negative, gate voltages [12].
Excimer laser annealing is the most promising of the crystallization processes. Several equipment producers are shipping commercial systems capable of accommodating 550 ? 650 mm substrates. In excimer laser annealing, the silicon film absorbs UV radiation from the laser. The film actually melts at temperatures approaching 1400?C and then forms grains when the laser pulse turns off. The rapid absorption allows use of short laser pulses (50 nsec) that affect only the surface layer, so the substrate remains well below the damage threshold. Impurities from the substrate do not diffuse into the polysilicon layer [4]. Excimer laser annealing has achieved grain sizes >1 ?m, and mobilities greater than 100 cm2/V-sec. Uniform laser performance remains a concern, however, and throughputs are low.
As shown in Fig. 5, larger grain sizes dramatically increase mobility. Grain size depends on substrate temperature, film thickness, and laser energy density. Preheating the substrate from room temperature to at least 360?C can increase mobility values by nearly 100% [4]. Ideally, the melt should extend almost to the bottom of the amorphous silicon layer but melt-through should be avoided, since it leads to a small grain structure. Super lateral growth occurs in this regime [8, 13]. Unfortunately, processing near melt-through requires very precise control over pulse-to-pulse repeatability Amorphous silicon films thicker than 80-100 nm require higher-energy densities and a shorter wavelength to achieve mobilities as high as in thinner films.
Figure 5. Effect of polysilicon grain size on field-effect transistor mobility.
Two excimer laser annealing techniques are in use today: overlapped scanning and single shot. Overlapped scanning was first introduced by XMR Inc. about 10 years ago. A high-power laser beam is passed through a series of mirrors and a homogenizer that convert the beam`s quasi-Gaussian intensity profile to a line-shaped and highly homogenized, spatially uniform top-hat profile. The beam can be adjusted, but is typically 0.1-10 mm wide by 200 mm long. Overlapping pulses scan the substrate, reducing the nonuniformities arising from pulse-to-pulse and spatial deviation of the irradiation energy [14]. The narrower the pitch, the higher the uniformity (and thus the higher the overlap rate) of each pulse [15]. While improving mobility and uniformity, high-overlap rates reduce throughput and laser lifetime. Throughputs of 20-30 substrates/hr are common in overlap scanning, with a 90-95% overlap.
The second excimer laser annealing approach, single shot, uses step-and-repeat pulses with a beam size as large as an 8-in. panel. This method uses a very high-power laser with 10-45 J of pulse energy, allowing the system to operate at a slower pulse rate. X-ray pre-ionization based on a secondary electron emission gun creates a more homogenous discharge. France`s Sopra SA claims improved uniformity and higher tool-up times for single-shot annealing. This approach reportedly improves pulse-to-pulse stability, increases amplification volume, reduces metallic dust pollution and improves system-to-system matching. The combination of longer pulse duration and better beam homogeneity gives a large grain size and uniform distribution.
The higher energies and wider beam size should require significantly fewer laser pulses, increasing the lifetime of the optics. Sopra estimates that a plant operating at a 20,000 plate/month capacity would require 20 billion laser pulses from a scanning system with a high degree of overlap, but just 5 million pulses for the single-shot approach [16].
Despite recent advances, LTPS developers typically name excimer laser annealing as a bottleneck and an immature process. The high overlap rate and short beam lengths relegate excimer laser annealing to less than 30 substrates/hr. Increased throughput will probably require multiple laser sources in a cluster-tool architecture. Uniformity is also a concern. According to one display manufacturer, the process window of LTPS is too small, even with overlapped scanning, due to the lack of uniformity of the line-beam density distribution and the lack of pulse-to-pulse stability [17].
Addition of a SiO2 or Si3N4 cap layer after the amorphous silicon deposition can further improve uniformity. The silicon/cap layer interface serves as another nucleation site and the resultant two-way solidification controls grain size variability relative to radiation energy [14]. The cap layer adds an extra step, but enlarges the allowable energy density deviation from a few percent to almost 10%. Significant work is still needed to make excimer laser annealing a robust process.
Other issues
Once a robust laser-annealing process is developed, other process steps will need to evolve to accommodate LTPS. New methods for hydrogen passivation, dielectric deposition, and dopant implant and activation will be required. Tighter design rules will demand more advanced photolithography tools. Part 2 of this article will discuss these supporting technologies. It appears on the Solid State Technology web site at URL http://www.solid-state.com, and will also be published in a future issue of the magazine.
Acknowledgment
The authors thank Barry E. Young of DisplaySearch for the preparation of the LCD cost model; Daniel Ferrin of Eaton Semiconductor Equipment Operations for the preparation of the graphs and drawings; and Mark Lucas of MRS Technology and Fred Kahn of Kahn International for manuscript review and suggestions.
References
1. DisplaySearch, Status and Forecast of Low Temperature p-Si Displays, May 1997.
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7. DisplaySearch, Interview Kam Law, AKT, January 1997.
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11. F. Harris et al., High Temperature RTP Processing on Large Area Glass Substrates for Manufacturing p-Si AMLCDs, Intevac White Paper, 1995.
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14. K. Sera et al., Proceedings, IDW `96, p. 85, 1996.
15. DisplaySearch, Interview with Yale Sun, XMR, February 1997.
16. M. Stehle, Laser Focus World, May 1996.
17. M. Okabe, Proceedings, IDW `96, p. 7, 1996.
JULIAN G. BLAKE received his AB degree from Amherst College, and his MAT and PhD degrees from Harvard University, where he worked on the optical properties of sputtered aSi:H and aSiGe:H films. He joined Eaton Corp. in 1984, and has been involved in process development and machine design of thin-film deposition, rapid thermal processing, and ion implant products. He is presently the technical director for Eaton Flat Panel Equipment, responsible for thin-film transistor process development and machine design of ion implanter products for flat panel displays.
MICHAEL C. KING received his PhD degree in solid state physics from Carnegie-Mellon University. He is currently GM of the Flat Panel Equipment Division at Eaton Corp. Prior to joining Eaton, he served as VP of technology at MRS Technology, where he gained extensive experience in lithography.
JAMES D. STEVENS III received his BS degree in management engineering from Rensselaer Polytechnic Institute, and his MS degree in operations research and applied statistics from Union College, Schenectady, NY. He joined Eaton Corp.`s Flat Panel Equipment Division as worldwide sales and marketing manager in August 1995. Prior to joining Eaton, he served as director of marketing for Rodel. Eaton Flat Panel Equipment, 108 Cherry Hill Drive, Beverly, MA 01915; ph 508/524-9229, fax 508/524-9233, e-mail [email protected].
ROSS YOUNG received his education at Japan`s Tohoku University and the University of California, San Diego`s Graduate School of International Relations and Pacific Studies. He founded the FPD market research firm DisplaySearch in early 1996. Prior to founding DisplaySearch, he held senior marketing positions in the FPD manufacturing equipment, FPD materials, and semiconductor equipment industries.