DUMIC 97: Beyond glass

04/01/1997

DUMIC `97: Beyond glass

Some 500 dielectricians gathered in Santa Clara, CA, recently to hear presentations on a wide variety of competing processes to replace SiO2 as the inter-metal dielectric of choice for deep-sub-micron process generations. The Dielectrics for ULSI Multilevel Interconnection Conference (DUMIC) explored integration issues in known processes and unveiled several radically new approaches that may be needed below 0.25 micron.

SiOF. Fluorine doping (SiOF) can easily reduce SiO2`s dielectric constant of 4.0 down to 3.5, and many papers covered process integration, reliability, and reproducibility experiments done on SiOF films. The DUMIC keynote address, by IBM`s Anthony Stamper, stated that SiOF and hydrogensilsequioxane (HSQ) are the only low-k materials that were developed early enough to be ready for incorporation into new 0.25-micron processes this year.

HSQ. HSQ films have k`s from 2.7 to 3.2 and most other properties are advantageous, but the brittleness of the standard material results in a 1-micron limit on thickness before cracking occurs. Researchers at IBM studied a variety of organic polymer additives to toughen the HSQ inorganic polymer matrix. Incorporating nano-scale polyamic esters increased the crackless thickness to 2 microns, and the films were stable to 425?.

CF. One of the more promising families of materials is PECVD carbon-fluorine (CF) films, since these new films have attractive thermal and mechanical properties for IMD integration. Also, since existing PECVD oxide systems can be simply modified to produce CF films, many large equipment companies with healthy R&D budgets see these films as a relatively low-risk, low-cost path. Applied Materials showed that their new Ultima HDP-CVD system could fill 0.35 micron 2:1 gaps with CF. Fujitsu, who first presented 2.4 k CF results at DUMIC`96, showed complete integration of CF with a glass transition temperature (Tg) >450?, SiOF inter-layer dielectric, and CMP of both layers (see figure).

Flow-fill. Electrotech, now a division of Plasma and Materials Technology (PMT), presented an entirely new approach to the deposition of low-k materials. In the "Flow-fill" process, gaseous precursors react to form a liquid on the substrate surface. Surface tension and gravity move the liquid to planarize the surface and to fill extremely tight gaps. A polymerizing bake step then forms the final film. Methyl silane is used for both the silicon and carbon sources to produce a final k of 3. The company claims to have filled 0.1-micron 4:1 aspect ratio gaps with film that is stable to 450? (suitable for integration with standard metallization).

STP. The most innovative process presented was also the simplest. NTT, along with researchers from Catalysts & Chemicals Industries, presented an SOG film Transfer and hot-Pressing (STP) IMD process that achieved fine-gap filling and global planarization in a single simple step. Perhydrosilazane is coated on a sheet and then transferred from the sheet to the wafer with heat and pressure under vacuum. After a 400?, 30-min. anneal, the film filled <0.5 micron gaps without voids. Though only at proof-of-concept, this incredibly simple process could prove to be very competitive.

Nanofoams. Nanoglass presented an overview of sol-gel NanoPorous Silica (SST, Feb. 1997, p. 38). Since these films produce the same material (silica) and use the same precursor (TEOS) as conventional dielectrics, they could be easily integrated if their porosity can be controlled. The porosity (% air with k=1 in oxide with k=4) is directly proportional to a lowering of k. Though nanoporous films have been produced with a k of 1.3, the best current research shows a k of 2 while maintaining film stability. Texas Instruments has completed nanofoam process integration including proof of stability at 700 atm and 400?. Moisture absorption may be a problem, so a cap layer may be needed.

Fujitsu has directly addressed the potential nanofoam moisture problem by reacting HSQ with a silica sol-gel to produce a hydrophobic porous SOG (HPS); they also showed that the pore size distribution was controllable between 10- and 50-nm diameter. Pore size distribution is critical to controlling the effective k inside of small device structures. Their film was stable to 450? at 2.0 microns in thickness.

Air gaps. In a classic example of "it`s not a bug, it`s a feature," researchers at Sandia Lab in Albuquerque showed that standard PECVD "keyholing" (characteristic closing off at the top of gaps) can be used to form voids deliberately in uniformly spaced gaps. It is uncertain how controllable such a process would be, since varying initial gap widths will result in varying void volumes and thus varying inter-line capacitance.

Dielectric roadmaps. Christopher Case, of Bell Labs/Lucent Technologies, gave a luncheon talk titled, "CMP, low-k dielectrics and copper change the look of future fabs." Copper processing may require separated fab areas, similar to the segregation that is currently used with CMP. In addition to molecular contamination problems, copper also creates hazardous materials, particularly as a result of the anticipated need for CMP.

If spin-on low-k dielectric and electroplated copper are integrated into a damascene process at 0.18 micron, one significant change would be a large reduction in capital equipment expenses. A typical 200-mm 20,000 wafers/month fab currently requires 65 multimillion dollar tools to deposit and etch interconnects. Case stated that new process flows could reduce that number to 45. - E.K.