Dielectric anti-reflective coatings for DUV lithography

03/01/1997

Dielectric antireflective coatings for DUV lithography

Christopher Bencher, Chris Ngai, Applied Materials, Santa Clara, California

Bernie Roman, Sean Lian, Tam Vuong, Motorola, Austin, Texas

High performance plasma-enhanced chemical vapor deposition (PECVD) dielectric antireflective coatings (ARC) can be readily designed by combining theoretical models from photolithography simulators with the manufacturing capabilities of silane-based plasma deposition chambers. By following the three steps outlined, the design of these ARCs can be made available to any semiconductor manufacturer for numerous applications. This paper demonstrates how a dielectric ARC was designed for aluminum metallization at DUV (248-nm) wavelengths. This ARC had <3% CD swing and <2% within-wafer linewidth uniformity variation.

While ARCs have been used to enhance IC lithography for years, the CD budget allowed in advanced sub-0.35-?m lithography is placing more demands on them. Design specifications of next-generation devices will require ARCs to suppress >99% of substrate-reflected light, meet stringent photoresist and device contamination requirements, and operate at extended ultraviolet wavelengths. Many of these requirements are not met by the conventional ARCs in production today.

During photolithography, light from the stepper is passed through a mask and the pattern is transferred to the wafer coated with photoresist. However, when the underlying film is highly reflective, as in metal and polysilicon layers, light reflections can destroy the pattern resolution by three mechanisms: a) off-normal incident light can be reflected back through the resist that is intended to be masked; b) incident light can be reflected off device features and expose "notches" in the resist; and c) thin-film interference effects can lead to linewidth variations when resist thickness changes are caused by wafer topology or nonflatness (Fig. 1) [1].

Over the past decade, semiconductor manufacturers have used many types of ARCs. These include bottom antireflective coatings beneath the photoresist to reduce substrate reflections, and top antireflective coatings deposited over the resist to reduce second-order reflections. Some photoresists have even been dyed in an attempt to absorb reflections [2]. Bottom ARC has emerged as the most effective in reducing reflections, while interfering the least with the photolithography process. However, with feature sizes shrinking well below 0.35 ?m, and stepper projection systems shifting to shorter wavelengths, many conventional bottom ARCs no longer maintain acceptable linewidth variations.

In recent years, several semiconductor manufacturers have proposed the use of CVD-deposited dielectric films as antireflective layers that can meet the requirements of sub-0.35-?m photolithography [3-7]. CVD processes allow film stoichiometry and optical properties to be easily tuned to specific needs, while also reaping the benefits of a conformal layer. These dielectric ARCs can be used for extending i-line lithography, or enabling DUV lithography. As alternatives to organic spin-on ARC, they have applications ranging from polysilicon gate to metal layer patterning.

CVD-deposited dielectric ARCs work by phase-shift cancellation of specific wavelengths (Fig. 2). This requires the simultaneous specification of three optical parameters: refractive index n, extinction coefficient k, and thickness d. Proper choice of these three parameters ensures that the transmitted wave that passes through the ARC film will, on reflection from the substrate, be equal in amplitude and opposite in phase to the wave reflected from the resist-ARC interface. In practice, phase cancellation requires very tight control of process parameters such that, for example, the thickness of the ARC is maintained to within 15 ?.

In contrast, conventional spin-on organic bottom ARCs rely on the absorption of reflected light through a relatively thick film (1000-2000 ?). Further thickness increases occur at patterned steps because of the self-planarizing nature of spin-on films. As a result, the necessary nonselective overetch during the ARC breakthrough etch produces CD control problems. Conversely, CVD-deposited dielectric ARCs are thin (200-300 ?), conformal to device features, and usually very selective during the ARC etch, so that CD control is easily maintained during pattern transfer (Fig. 3).

Figure 1. Resolution breakdown mechanisms from substrate reflections.

Dielectric ARC design

To demonstrate design of a near-zero reflectivity dielectric ARC film for any application, we will examine the case of an ARC film for aluminum at DUV wavelengths. Bare aluminum can have reflectivities of >90% at DUV wavelengths, making it a difficult film to pattern. Additionally, traditional aluminum ARC layers, such as titanium nitride, may fail to meet the optical properties or resist contamination requirements demanded by DUV lithography [8, 9].

Step 1. Simulation. The first step in the design of a high performance ARC is to determine the required optical properties (n, k, d) for total phase-shift cancellation. A desktop photolithography simulator, in this case Prolith/2 [10], can simplify optimization of the ARC for a given substrate film stack.

Typical simulation input variables include stepper parameters, mask pattern details, resist and developer types, and pre-and postexposure bake conditions. Of these parameters, only the wavelength, substrate film stack, and resist index of refraction are critical to the design of the dielectric ARC. These parameters will determine the substrate reflectivity, which can be minimized by adjusting the dielectric ARC optical constants n, k, and d. In the straightforward case of aluminum, neither the underlying film structures nor the aluminum film thickness plays a critical role, because the extinction coefficient of aluminum is high enough (2.35-2.94 k at 248 nm) so that any DUV will attenuate rapidly. The accurate predictions of resist profiles and CD control, however, require attention to all the input parameters. Second order effects, such as the angular distribution of substrate illumination, have not been considered in optimization of the ARC properties.

By running simulations in n, k, and d space, we can calculate substrate reflectivities at the resist-ARC interface and assemble contour maps (Fig. 4) to predict the performance of various ARC films. A reflectivity contour map, such as the one created here for aluminum films, is the primary tool needed to tune the CVD process to meet complete phase-shift cancellation conditions with the dielectric ARC film.

Step 2. Process targeting. Having established a substrate reflectivity contour map, we began to characterize a dielectric CVD process that could deliver n and k constants near a zero reflectivity contour. Silicon oxynitrides represented the best candidate ARC material family for several reasons. First, silicon oxynitrides possess an ideal range of optical properties that meet many simulation-targeted requirements (Fig. 5) [7]. Second, plasma-deposited SiOxNy has an amorphous structure and can, therefore, be fine-tuned to specific n and k requirements by varying the Si, O, and N contents of the film. Finally, silicon oxynitride films have been widely used in semiconductor manufacturing for years, and are compatible with most devices and process integration schemes.

This study used an Applied Materials single-wafer PECVD silane-based, lamp-heated chamber to tune the silicon oxynitride processes. To measure the wavelength-specific refractive indices and extinction coefficients of the deposited films, we used an n&k Analyzer [11-13], which also yields accurate measurements of film thickness.

By adjusting the gas flow ratios in the plasma, we developed n and k process trends intersecting with the reflectivity contour lines. Two such process trends were added to the contour map in Fig. 6. The recipes at the points of intersection between the process trends and the contour line of zero substrate reflectivity should, according to simulation, yield the highest performing dielectric ARCs.

We returned to the resist profile simulator to examine the performance differences of dielectric ARCs with 0%, 1%, and 3% substrate reflectivity. CD swing curve simulations [14] determined how well a resist linewidth will be maintained as the resist thickness varies, as with resist spun over device topography. Figure 7 predicts CD swing curves for ARCs with 0%, 1%, and 3% reflectivity, yielding swing ratios of <1%, 17%, and 30%, respectively. The ARC film designer can then balance the size of the acceptable PECVD process window in n, k, and d space with the allowable CD budget.

The sensitivity of the linewidth control to the substrate reflectivity (Fig. 7) illustrates the need for ultra-high performance ARCs when patterning with chemically amplified DUV photoresists. For processes requiring even modest CD budgets, ARC films will need to maintain consistent substrate reflectivities in the sub-1% range, placing tight constraints on the control of n, k, and d. The ability to accurately control the deposition of very thin films (~250 ?) is a fundamental advantage for PECVD dielectric ARCs in sub-0.35-?m lithography.

Step 3. Lithography testing. Sample wafers were processed, patterned, and measured for CD swing control to verify the simulation predictions and test the ARC performance. Ten bare silicon wafers were deposited with 6000 ? of blanket aluminum followed by a dielectric ARC. The properties of the ARC were measured as n = 2.16, k = 0.88, and d = 254 ?. The test wafers were then spin-coated with 10 varying thicknesses (0.55-0.7 ?m) of undyed APEX E resist to simulate resist thickness variations such as those over device topography. DUV patterning was performed with 0.35- and 0.3-?m nominal CD lines, and linewidth vs. resist thickness was measured. Nine point measurements within each wafer were taken on a KLA 8000 with the wafer-averaged CDs plotted vs. resist thickness. As a control group, an additional set of wafers was simultaneously processed with a traditional 250-? titanium nitride ARC.

The experimental results (Fig. 8) clearly showed the titanium nitride ARC producing a classic CD swing, measured here at 9%. No discernible CD swing could be detected with the dielectric ARC, with the 3% linewidth change appearing to result primarily from resist bulk effects and measurement scatter. Although the measured linewidths tended to be slightly larger than the targeted linewidths (0.32 vs. 0.3 ?m), this can be attributed to an exposure dose setting that is not optimized for the ARC film. The 9 point within-wafer measurements showed the CD uniformities to be less than 2% for all wafers. The CD swing and uniformity data confirm that PECVD-deposited ARC films meet the control requirements of an ultra-high performance ARC.

Resist profiles were examined to determine the extent of footing caused from DUV photoresist interface contamination. The traditional TiN ARC has a large footing problem; the dielectric ARC film has no footing or DUV resist contamination (Fig. 9).

Figure 2. Phase-shift cancellation by optimization of a bottom dielectric ARC.

Figure 3. Demonstration of resist loss during pattern transfer to ARC layers: a) organic spin-on ARC; and b) dielectric ARC.

Figure 4. Contour map of 0%, 1%, and 3% substrate reflectivities for 220-, 240-, and 265-? ARC films. ARC film requirements are for 248-nm aluminum.

Figure 5. Refractive index of various materials at 248 nm [7].

Figure 6. Overlapping plots of n and k process trends and 0%, 1%, and 3% substrate reflectivity contours for 220-, 240-, and 265-? ARC films. Intersection points along the zero reflectivity line represent an optimized bottom ARC. ARC film requirements are for aluminum at 248 nm. The recipes at the points of intersection between the process trends and the contour line of zero substrate reflectivity should yield the highest performing dielectric ARCs.

Figure 7. Simulated CD swing curves for dielectric ARC films of 0, 1, and 3% substrate reflectivity. Since the model predicts that just 1% reflectivity results in 17% CD variation, control of the ARC process is critical.

Figure 8. Measured CD swing curves for dielectric ARC films and TiN using APEX E photoresist at DUV wavelength. The dielectric ARC has superior performance at both 0.35- and 0.3-?m linewidths.

Figure 9. Photoresist profiles showing that a) traditional TiN ARC can cause footing with chemically amplified DUV resists, whereas b) the dielectric ARC has no footing or resist contamination.

Conclusion

PECVD-deposited dielectric ARC testing demonstrates its application in critical photolithography. The design of these ARC layers is facilitated by photolithography simulators. The required level of process control is within the manufacturing capabilities of single-wafer architecture deposition chambers. By following the three outlined steps (simulation, process targeting, and lithography testing), the design of similar ARCs is readily available to semiconductor manufacturers for numerous applications.

References

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10. C. A. Mack, Prolith/2 v.4.05a, Finle Technologies, Austin, Texas.

11. A.R. Forouhi, I. Bloomer, n&k Analyzer, n&k Technology, Santa Clara, California.

12. A.R. Forouhi, I. Bloomer, "Optical Dispersion Relations for Amorphous Semiconductors and Amorphous Dielectrics," Phys. Rev. B, p. 7018, 1986.

13. E. Ibok et al., "Optical Characterization of Amorphous and Polycrystalline Silicon Films," Solid State Technology, Vol. 38, No. 8, pp. S11-S20, August 1995.

14. C. A. Mack, "The Lithography Tutor: Swing Curves," Microlithography World, Vol. 3, No. 3, pp. 23-25, Summer 1994.

Contact Christopher Bencher, Applied Materials, 3050 Bowers Ave., M/S 1263, Santa Clara, CA 95054.