Stoking the productivity engine with new materials and larger wafers
03/01/1997
Stoking the productivity engine with new materials and larger wafers
Dave Anderson, SEMATECH, Austin, Texas
Wafer diameter increases and device feature-size decreases have been critical to the success of the semiconductor industry. The productivity gain brought about by increasing the number of chips on a wafer and the number of active elements within a chip continues to drive the growth of end-user markets.
Starting with the 300-mm generation, most manufacturing equipment will be dedicated to only one wafer size. Wafer generations will be extended to allow for equipment investment paybacks. Extrapolations of historical trends predict a jump to 450-mm wafers by the year 2010.
Past linewidth reductions called for the development of at most one new material per generation. However, deep submicron processing will require multiple new materials at each successive generation. This will place an unprecedented burden upon process development.
Raw materials are the foundation of all industrial enterprise. The strategic value of the materials industry is indisputable, even though its entire direct annual value is relatively modest at about $20 billion (Fig. 1). This relatively small industry supports a customer base nearly 10 times its size in the semiconductor and semiconductor equipment markets. The semiconductor industry, in turn, supports a much larger electronic equipment industry, which then sustains the worldwide electronics-dependent industrial base of roughly $15 trillion. The potential impact of a supply disruption at the base of this value chain is tremendous.
The productivity engine
After a brief DRAM price-driven market correction in 1996, the semiconductor industry is once again on course for a period of sustained growth and prosperity. In the race to become a $300 billion industry near the turn of the century, many increasingly difficult technology challenges must be resolved.
Three decades of IC market growth have been led by the industry`s ability to continually improve the cost/DRAM bit or logic function by 25-30%/year. This steep productivity curve has enabled continued expansions in electronics markets through reduced prices of goods such as PCs. Keeping this productivity engine on track presents a formidable challenge to the entire semiconductor industry supply chain.
Past productivity improvements were attained by four primary contributions: increased capital equipment utilization, die yield improvements, larger wafer sizes, and shrinking device feature sizes. Increasing overall equipment effectiveness, the percentage of time equipment is adding value to the wafer, is the best opportunity for IC manufacturers to improve productivity. Yields have typically been increased to >90%, and only modest additional improvements can be expected. Larger wafers and smaller features will continue to play important roles.
300 mm and beyond
The overall magnitude of productivity gains attainable through increasing wafer diameters has decreased with each successive generation because of higher silicon costs and extended wafer size life-cycles. However, the impending conversion to 300 mm, beginning in 1998-2000, is still expected to provide manufacturers with at least a 2-4%/year lower IC cost/cm2. This will be achieved through a roughly 2? increase in die/wafer and improved edge-packing efficiency.
Historical analysis of silicon consumption indicates a recent significant change in the wafer generation life cycle. Prior to 200 mm, all previous wafer diameter increases have been accomplished in binary clusters, i.e. 38-51, to 75-100, to 125-150 mm. Each of these binary generations started with approximately eight years of production at the new 33% diameter increase followed closely by 16 years of the 50% increase.
The anomaly generation, of course, was 125 mm, which never really reached maturity before being ousted by a much stronger 150-mm diameter. In retrospect, modeling could have shown that the 125-mm generation should not have occurred and that the industry should have converted directly from 100- to 150-mm wafers.
Historically, most production equipment has been viable for at least two wafer size generations, allowing equipment suppliers approximately 24 years to recoup investments in tool development. However, most current 200-mm equipment will not be retrofittable to 300-mm sizes, and most new 300-mm designs will not be backward compatible.
From extrapolations of historical models and through statistical regression, it is evident that each new size generation will remain in production for 24 years. This 24-year single-diameter life cycle is extremely important for determining the timing for equipment and materials development as well as the payback period for R&D investments (Fig. 2).
The single diameter (50% increase) life cycle model predicts that the next wafer size after 300, with development beginning around 2010, will be 450 mm. In order to maintain the overall compound annual growth rate in worldwide silicon consumption, a move to 400 mm instead of 450 mm would reduce the time allowed to recoup equipment investments by approximately six years.
The overall die/wafer benefit of conversion to 300-mm wafers is clear. Offsetting some of the initial productivity savings, however, is an increased silicon cost/cm2. The technical challenges and the physics associated with crystal-pulling results in a reduced yield of potentially good wafers from raw polysilicon. Tightened electrical specs have reduced the "sweet zone" in the middle of the ingot that yields prime wafers, though volume experience should improve this limitation. Larger diameter wafers also need to be thicker to maintain rigidity, so fewer wafers can be produced from the same ingot length.
The menacing potential for an industry conversion to epitaxial silicon for DRAM production would also increase the cost of silicon for IC manufacturers. Even though epi becomes somewhat more cost effective with larger diameter wafers, the current premium is nearly 2? the cost of prime wafers.
Figure 1. The relatively modest $20 billion materials industry supports the $15 trillion worldwide industry base.
Figure 2. This 24-year single-diameter life cycle is vital for determining the timing for equipment and materials development, as well as the payback period for R&D investments.
New materials
Shrinking design rules are expected to continue to provide approximately 12-14%/year reduction in IC manufacturing cost. It is fully expected that 0.25-?m geometry devices will be in full production this year. Ever-increasing transistor densities and chip speeds require entirely new lithography techniques, interconnect schemes, etc. Materials, once considered to be readily available enablers, are rapidly becoming critical development challenges.
Though industry roadmaps prescribe that overall cost/function must continue to decrease, the materials component of this cost (as a percentage of total manufacturing cost) is on the rise. Materials could contribute to as much as 30% of the cost of a finished wafer by the year 2000 (Fig. 3), replacing equipment depreciation as the single largest expense. This distressing increase is generated by several fundamental, yet unfortunately coincident, technology hurdles that must be overcome. New materials, other than larger wafers (previously discussed), are expected to be the main component of cost increases.
As lithography field size increases, photomasks and lenses must keep pace. Significant challenges are posed to fused silica production, and photoblank manufacturing and polishing for 9 ? 9 photomasks. Potential degradation of attenuating films, pellicles, and even lenses, due to exposure to highly energetic wavelengths, is not yet fully understood. Photoresists are no longer viable for more than a single device generation. In order to minimize capital outlay, mix-and-match litho technology will call for the use of several resists within the same process flow. All of this places additional development strain on suppliers, and the burden of higher materials costs on users.
An intriguing area for future development will be in device interconnects. Typical transistor density will likely reach 1 billion/chip by 2010; all of these transistors must be connected for the device to be useful. Each successive design rule generation adds more metal and dielectric layers. These connections will need towering metal and dielectric structures that require new materials.
As interconnects move from aluminum conductors and oxide inter-layer dielectrics to copper and low-k materials, fundamental physical limits of traditional architectures are approached. Interconnect delays are the dominant speed limitation for current ICs. Copper and low-k dielectric buy one or two generations (Fig. 4), but new inventions will be required to move below 0.13-?m linewidths. The most optimal metal interconnect structure is silver lines with air dielectric (k = 1), which is unmanufacturable and only marginally superior to copper and low-k. It appears that radical changes, such as superconductor- or optical-interconnects, will be required below 0.13 ?m (year 2003).
Ever larger contact and via aspect ratios require alternative source materials for liners and barrier layers. New materials must be cost effective, and capable of deposition at low temperatures for compatibility with low-k dielectrics. Higher reliability and lower contact resistance are also desirable.
Chemical-mechanical planarization (CMP) is another rapidly evolving technology that will significantly increase the cost of fab materials. Developments of multiple new CMP consumables (pads and slurries) for soft metals are required. Consumable life, materials cleaning capability, and chemical and colloidal stability are only a few of the cost contributors that must be improved.
Though one new material has historically been allowed into production with each new device generation, the current acceleration of new material introductions is unprecedented (Fig. 5). Device manufacturers face the potentially unmanageable task of simultaneously developing processes for several completely new materials. Complex matrix experiments will be needed to define multidimensional process specifications.
Materials interactions and device reliability issues must not be overlooked in the move to high-volume production. Difficulties could be further exacerbated by a separation of process technology between logic and memory manufacturers, causing each to pursue separate solutions. Advanced materials specs and standards are critical to controlling the costs (both intellectual and capital investment) of materials development.
Environment, safety, and health considerations must also be considered with new materials introductions. Provision for material disposal and/or reclaim, adoption of replacement chemicals and gases, and process development for recycling CMP slurries are all of concern.
Figure 3. Materials could contribute to as much as 30% of the cost of a finished wafer by the year 2000, replacing equipment depreciation as the single largest expense.
Figure 4. Copper and low-k dielectric buy one or two generations, but new inventions will be required to move below 0.13-?m linewidths. (Source: Mark T. Bohr, Proc. of the 1995 IEEE IEDM, pp. 241-242.)
Figure 5. Though one new material has historically been allowed into production with each new device generation, the current acceleration of new material introductions is unprecedented.
Conclusion
Future technology requirements have been defined in concert with the National Technology Roadmap for Semiconductors (NTRS). Advancement can only be achieved through the timely development of new materials. This development demands tightly integrated process/materials R&D programs with active involvement of all levels of the semiconductor value chain.
The tremendous industry growth of 1993-1995 continued amid persistent concern that there could be significant supply shortages of several fundamental materials, including silicon wafers, photomasks, quartzware, polysilicon, packaging materials, and even stainless steel and Teflon. As the industry resumes growth, accurate capacity/expansion forecasting and continuous communications with suppliers will maintain a well-balanced flow of new materials.
Due to relentlessly increasing product complexities, the materials solutions for future technology generations will require significant multidisciplinary cooperation. Not only are the number of new materials increasing, but the materials required are more exotic than ever before. Future technology requirements may well be beyond the capabilities of many established materials and materials suppliers.
Clusters of new materials require parallel efforts in research, development, and manufacturing to meet the timing requirements of the NTRS. Multiple materials interactions, and their potential side-effects, must be fully comprehended. The entire semiconductor industry value chain must pull together to bring forward the availability of cost-effective materials solutions in order to keep the productivity engine on track.
DAVID ANDERSON received his BSMSE degree in materials science and metallurgical engineering and his MS degree in business administration from Purdue University. He is a senior marketing manager at National Semiconductor Corp. Presently, he is on assignment as manager of critical materials and competitive analysis at the SEMATECH consortium in Austin, TX; ph 512/356-7076, fax 512/356-3065.