W-plug via integration issues

02/01/1997

W-plug via integration issues

Subhas Bothra, Dipu Pramanik, Dan Baker, Milind Weling, Calvin Gabriel, Harlan Sur, Xi-Wei Lin, VLSI Technology Inc., San Jose, California

In the submicron regime, packing density in integrated circuits is dependent on metal interconnect density. Interconnect design rules are, therefore, scaled very aggressively from one generation of technology to the next. In addition, more levels of metal are added to provide a larger area for interconnects, along with greater flexibility in routing. Figure 1 shows a scanning electron microscope (SEM) cross-section of a five-level metal backend structure. Electrical connection between the various metal layers is provided by vertical interconnects commonly referred to as vias.

The via structure has evolved considerably over the last decade. Nonfilled vias (Fig. 2a) have been used in the past. In this case, the top metal layer comes in direct contact with the lower metal layer at the via opening. As seen in Fig. 2a, the metal step coverage over the via sidewall and bottom is reduced and degrades further as the via aspect ratio (the ratio of via depth to via diameter) increases. Proper shaping of the vias, such as the tapering indicated in Fig. 2a, reduces the effective aspect ratio; this approach has been used effectively down to 0.5-?m technology.

As vias get even smaller, however, the metal step coverage degradation becomes acute. In the filled via approach (Fig. 2b), the via opening is completely filled by conformal chemical vapor deposition of tungsten. The resulting tungsten layer over the oxide can be removed by a blanket plasma etch process or by chemical mechanical polishing (CMP), leaving a completely filled via. An alternative method to achieve a filled via is based on the reflow of Al alloy at high temperature [1] and at high pressure [2].

Figure 1. SEM cross-section of a five-level metal interconnect structure; vias are indicated as V1 through V4.

Figure 2. SEM cross-section of an a) nonfilled via; and b) filled via.

The shape of unfilled vias creates difficulties when two or more are stacked directly above each other. The resulting via aspect ratio is very large, leading to formidable problems with via etch and via step coverage. In comparison, Fig. 2b clearly shows that filled vias can be easily stacked by using an identical via process for the next level. Stacked vias result in considerable area savings: ~15% in a triple-level metal system at 0.35-?m technology design rules.

Via integration in a multilevel metal (MLM) scheme is affected by many of the choices made in the metal system, the dielectric system, and the planarization process. This paper details the integration issues arising from the development of a deep submicron process that allows stacking of vias by using a tungsten plug-filled via in a SOG etchback-based stack with a TiN/AlCu/TiN metallization scheme. The following discusses the impact of photolithography, plasma etch, glue layer, metal stack, IMO stack, and planarization on the via integration.

Via patterning

Via diameter and depth are critical issues, as they determine the feasibility of using a particular glue layer and fill technology. For via diameters in the range of 0.4-0.6 ?m and aspect ratios up to 3:1, both CVD W and Al plug-fill are viable. In the case of a conformal deposition process such as CVD W, a via slope, q, of =90? is necessary for a void-free fill.

An underlayer is required prior to via-fill, a glue layer for CVD W, and a wetting layer in the case of Al plug-fill. The via slope and aspect ratio influence deposition of the underlayer. A tapered via allows improved coverage by the underlayer when a sputtering process is employed, while a conformal CVD process is able to provide adequate coverage over a wider range of slopes. Normally, Ti is preferred as a wetting layer for Al plug applications and TiN as a glue layer for CVD W-fill. In many situations, a combination of these films may also be used for optimum performance. These underlayers can be deposited by both sputtering and CVD. The step coverage provided by standard sputtering is adequate for 0.35-?m technology. Collimated sputtering or CVD will be required for smaller via sizes.

Figure 3. Effect of sputtered TiN on the via slope.

The sputtered film, however, creates a thicker layer at the via top compared to the via bottom (Fig. 3). If a vertical via is employed for W plug-fill, the sputtered glue layer will give the via a re-entrant profile prior to CVD W, and a void free W-fill in the via cannot be obtained. A tapered via is thus preferred, but the top diameter is constrained by design rules (i.e., interconnect density) so the bottom area of the via must be reduced. For a 0.5-?m via with an aspect ratio of 2:1, an 85? slope increases the via resistance by a factor of ~2.0. Thus the via photo and etch processes have to be optimized to provide the required via shape with tight control of via slope between 86-88?.

High resolution i-line resists with a wide range of bleachable and nonbleachable transmission parameters were evaluated and compared to simulation results of the resist profiles. The chosen photoresist met the requirements of focus latitude for minimum design rules, minimization of proximity effects, and a resist profile that facilitated via etch process. For improved process repeatability, a vertical resist profile is preferred and the via slope is tailored by the etch process. Our work used a two-step process with varying ratios of CF4 and CHF3 in the process gases [3]. This process allows three degrees of freedom in optimizing the via profile: the time division between the two steps (the total time is constrained by the via depth and overetch requirements), and the gas ratios in each of the two steps. Optimum profiles can be obtained while maintaining reasonable selectivity to underlying films.

Figure 4. W deposition into the via where AlCu of the underlying metal is attacked by the solvent strip.

A side effect of the etch process is the formation of "polymer" at the via bottom. Different wet chemical strips were evaluated for polymer removal with both strip time and solvent temperature as variables. The solvent found to remove this material, however, also attacked and gouged any exposed AlCu (Fig. 4).

W then deposits on the gouged AlCu and increases via resistance (Table 1). Two split lots were processed identically, except that the top TiN film thickness at metal 1 was varied between 500-1500 ?. In the case of the 500-? TiN layer, gouging of the AlCu meant that the TiN glue

layer was not continuous and the via resistance was ~80% higher, probably due to direct contact between WF6 and AlCu at the via bottom. The 1500-? TiN is thick enough to prevent this. Thus, to avoid exposure of AlCu during via etch, it is important to control both etch selectivity of oxide to TiN and TiN film thickness.

Via glue layer

There are two options for the glue layer in the TiN/AlCu/TiN metallization scheme, a single TiN layer or a Ti/TiN stack. A Ti layer is preferred, as it helps to reduce any remaining oxide at the via bottom; however, a single TiN process is simpler. Ti, because of its high reactivity, also results in good adhesion between the oxide and the metal layers. Commercially available methods for depositing the TiN film include standard sputtering, collimated sputtering, and CVD.

For the via dimensions discussed here, standard sputtered TiN is adequate. Collimation or CVD would allow the via profile to be vertical, thus increasing the via area at the bottom as previously discussed. However, in both sputter-deposited TiN films, the thickness and use of the optional Ti layer is limited by the inferior TiN deposited on the sidewalls and top corners. "Volcanoes" can form (Fig. 5) when the via profiles, Ti thickness, and TiN thickness are incompatible. While a CVD TiN film alleviates this concern, current CVD TiN processes are adequate for contact fill, but use too high a temperature for via applications (significant advances are being made by several vendors in this area).

Figure 5. Volcanoes on the via where the Ti underlayer is thick and the TiN barrier has failed.

The barrier failure of the glue layer usually occurs at the top corner of the via and increased barrier failure occurs with thicker Ti. A 500-? Ti /500-? TiN glue layer always resulted in barrier failure and volcanoes. A 200-? Ti/500-? TiN glue layer did not result in volcanoes, but showed higher via resistance, indicating that there was still an interaction between WF6 and Ti. Table 2 shows a summary of the impact of Ti in the glue layer on via resistance using sputtered TiN at metal 1. Splits #3 and #4 using a top TiN of 1500 ? clearly show increased via resistance when Ti is used under the TiN as a glue layer. When the top TiN is reduced to 500 ?, the impact of the Ti is increased because of an interaction with AlCu as discussed earlier. In this case, the Ti is also exposed to WF6 at the via bottom due to discontinuities in the glue layer.

Metal stack

The top of the underlying metal stack may interact with the via during via etch. If the via etch is allowed to penetrate through the top TiN, then the interactions between the metal stack and the via process have to be considered. The effect of the thickness of the top TiN in metal 1 on the via resistance has already been discussed. If a top TiN thick enough to provide a via etch stop is used, then the metal stack and via interaction can be decoupled.

Where a higher electromigration resistance is desired, a Ti layer must be included in the metal stack. This Ti layer can be introduced in two different places for a metal stack of either (bottom)TiN/Ti/AlCu/TiN(top) or (bottom)TiN/AlCu/Ti/ TiN(top). Improved electromigration has been reported for both structures. If the Ti is placed above the AlCu layer, its impact on the via resistance has to be considered (Table 3). The 200-? Ti layer reacts with Al to form a TiAl3 layer and provides an additional overetch margin for the via etch and clean.

When plasma etch removes blanket W, the inevitably finite overetch leads to W recesses in the vias. These recesses can create problems for subsequent metal deposition, whether for traces or stacked vias. In a stacked process, the via etch must be able to fully clear this region and thus will require a longer oxide overetch. Glue layer deposition and W-fill are also more difficult in even slightly recessed vias. To avoid these problems, W etchback and metal deposition must be optimized to provide a smooth metal profile over the via. A higher metal sputter temperature allows some smoothing through reflow of the metal.

IMO process

The IMO stack has significant impact on the via integration. In the SOG etchback scheme used here, the potential for via poisoning (Fig. 6) mandates that no organic SOG is exposed during via fill. This restriction can be eased by the use of a via oxygen plasma treatment [4, 5] or the use of a degas process followed by the formation of a solid CVD TiN barrier. If an inorganic SOG or a gap-fill CVD oxide is used in the IMO, then via poisoning is avoided completely (Fig. 7).

Figure 6. Via poisoning (unfilled via) due to organic SOG exposed at via.

Figure 7. Inorganic SOG used in the IMO showing no via poisoning.

Even when organic SOG is completely removed directly over the metal areas, SOG may be exposed at edges if vias are not fully landed (Fig. 8a). To avoid this failure, the design rules must be relaxed so that vias are fully landed. For an inorganic SOG or a gap-fill CVD oxide process (Fig. 8b), material exposure does not cause a problem during via-fill, and tight design rules with respect to via/metal overlap can be maintained.

The potential for a via to fall off an underlying metal is most likely in the case of a stacked via structure (Fig. 9). The metal (shown here as M2) is often not a line but a square of minimum dimensions used simply to connect via1 to via2. This minimum square is the worst case from a photolithography point of view, as it has the least DOF margin and therefore suffers from the largest critical dimension loss. With further shrinkage in design rules for 0.25-?m technology, it will be necessary to allow the via to fall off the metal below, and the situation may occur for every via.

Figure 8. With a) an organic-based SOG scheme, the via must not fall on the SOG pocket in the intrametal space; however, this is allowed in b) a gap-fill CVD oxide scheme.

Figure 9. Stacked contact/via 1/via 2 structure.

The planarity of the IMO also dictates the amount of overetch needed at the W-plasma etchback process [6]. Overetch directly translates to via plug recess and becomes an important factor in the processing of stacked vias, as previously discussed. With proper optimization of SOG planarization and W-plasma etchback, a stacked via process at 0.35-?m rules can be achieved. With further decreases in minimum design rules, the process margins become narrower, and future process technology will require the incorporation of a CVD gap-fill oxide coupled with CMP of the W plug.

Conclusion

If TiN layers are too thin, they are inadequate barriers; if they are too thick, they increase contact resistance. Organic SOG films can induce via poisoning when the bottom of an etched via overlaps the metal contact. Stacked vias, necessary to maintain tight design rules, magnify the effects of overetch. Most of the issues discussed are relevant to other submicron processes, including aluminum plug-fill, nonetchback SOG, and gap-fill CVD-based IMO. Successful stacked via integration requires a thorough understanding of interactions between most of the backend processes and equipment.

References

1. N. Ito, Y. Yamada, Y. Murao, D.T.C. Huo, Proceedings of the Eleventh Intl. VMIC Conf., p. 336, 1994.

2. P.J. Holverson, et al., Proceedings of the Twelfth Intl. VMIC Conf., p. 537, 1994.

3. M. Weling, D. Baker, S. Bothra, Proceedings of the Twelfth Intl. VMIC Conf., p. 570, 1995.

4. S. Ito, Y. Homma, E. Sasaki, S. Uchimura, H. Morishima, J. Electrochem. Soc., Vol. 137, No. 4, p.1212, 1990.

5. J. Waeterloos, et al., Proceedings of the Second Intl. DUMIC Conf., p. 52, 1996.

6. C. Gabriel, M. Weling, S. Bothra, Proceedings of the Second Intl. DUMIC Conf.,

p.153, 1996.

SUBHAS BOTHRA received his PhD degree in electrical engineering from Rensselaer. He is manager of interconnects and works in MLM process technology at VLSI Technology Inc. 1109 McKay Drive, MS/02, San Jose, CA 95131; ph 408/434-3000, fax 408/922-5393.

DIPU PRAMANIK is director of process technology at VLSI. He is responsible for the development of process modules for 0.25-?m and 0.18-?m technologies, including advanced lithography, plasma etch and CMP, diffusion advanced metallization, and defect engineering.

DAN BAKER received his BS and MS degrees in chemical engineering from Texas Tech University. He has worked in photolithography process development at VLSI for six years.

MILIND WELING received his MS degree in electrical engineering from the University of Hawaii. He is responsible for developing deep submicron chemical mechanical polishing processes at VLSI Technology Inc.

CALVIN GABRIEL received his MS and engineer`s degrees in chemical engineering from MIT, and his MS degree in electrical engineering from Stanford University. He is manager of plasma etch and CMP in the technology development group at VLSI.

HARLAN SUR is staff process development engineer with VLSI. His work includes physical and electrical device/process characterization, defect analysis, and advanced test structure design.

XI-WEI LIN received his PhD degree in solid state physics from the University of Paris at Orsay. He is a staff engineer at VLSI, where he works on metallization and salicide processes.