The influence of PCB parameters on CSP assembly and reliability
09/01/2000
Assembly process parameters, material selection and board geometry affect yields and reliability during attachment of CSPs onto organic motherboards.
BY ANTHONY A. PRIMAVERA
With the continual miniaturization of electronic components and overall systems, the interconnection of the printed circuit board (PCB) and the component - namely the solder joint - becomes smaller as well. This reduction in the size of the joint places more demands on the mechanical properties of the solder to ensure joint robustness. In addition to footprint size reduction, there is an emphasis on total space reduction, often leading to reduced size in the packaging of the silicon die. As surface mount technology (SMT) migrates toward smaller package dimensions, the physical and thermal characteristics of each packaging material become more critical.
Significant differences between properties within a package (from layer to layer or between the carrier and the die) can cause extensive internal stresses. Once mounted to a PCB, the solder joint typically must absorb all strains induced by the expansion of the package and PCB in thermal excursions. For traditional SMT devices, such as quad flat packages, the leads and solder joints provide the compliance needed to compensate for the mismatch in coefficient of thermal expansion (CTE) of the package and PCB. However, in area array devices, such as ball grid arrays (BGAs) and chip scale packages (CSPs), the joint alone must provide CTE mismatch compliance. As joints become smaller, their quality becomes more critical. Physical defects (e.g., poor solderability, excessive intermetallic formation and voids) can have a negative impact on joint robustness and soldering yields.
 Figure 1. Assembly yield causes and effects. |
Because most CSPs are smaller versions of BGA packages, the critical parameters that affect BGAs should be the same as for CSPs. Factors that affect area array assembly yields can be classified into several main categories, including assembly materials, PCBs and components, process methods, joint quality and human performance.
The assembly materials category can be subdivided further into solder paste and flux-related parameters, such as applied volume, reflow parameters, fluxing and solder paste deposition methods, and handling and storage conditions. The most critical issue within this category is the proper fluxing of the attachment surfaces and the creation of proper metallurgical bonds during the reflow operation.
 Figure 2. CSP desorption curve. |
The PCB category contains many influences on the overall solder joint reliability, including pad metallurgy, board thickness, pad size, base material, via formation technology, routing method (via-in-pad vs. fan-out), PCB layer count, solder mask technology, and pad definition vs. mask definition. The PCB parameters that influence CSP reliability will be the focus of this article. The components subgroup parameters that influence the assembly reliability may include construction (flex vs. rigid carrier, etc.), die-size-to-package ratio, solder ball size, attachment pad size and definition, base materials, package size, and ball configuration.
The process methods category is influenced heavily by the individual steps in the assembly (i.e., standard double-side assembly or mixed assembly with solder wave pass). Factors such as reflow methodology (convection vs. infrared (IR) radiation) and atmosphere will affect solder-wetting, joint formation/shape and the presence of voids. Joint quality is affected by almost all assembly variables but is influenced strongly by the type of paste/flux, attachment pad metallurgy and reflow conditions. Highly irregular-shaped joints, excessive voiding and poor solderability can lead to early failures. Human performance factors that often are overlooked may include operator education and training, in addition to human error.
One advantage of the CSP package is its compatibility with the existing standard surface mount PCB assembly environment. Typically, a CSP assembly process relies on solder-paste deposition through stencil-printing, component placement and mass reflow soldering. Factors that may affect the assembly process yield can be divided into four main categories, including human performance factors, equipment and tooling, materials, and process methods. Figure 1 illustrates the factors that influence CSP assembly yields.
Human Performance Factors
Operator input, including handling, training, education, setup and quality control, can affect the yield of the assembly process.
 Figure 3. Small ball CSP open because of package warpage and insufficient solder ball volume. |
Handling: Improper handling(manual or automated) can be detrimental to the integrity of components on the assembly. This issue becomes extremely important when automatic assembly transportation systems (conveyors) are not implemented. Improper manual handling (especially after the component placement process) may result in component misalignment. Consequently, defects (such as opens or bridges) can occur after reflow soldering. When handling moisture-sensitive packages, adequate handling strategies should be implemented to prevent devices from excessive moisture absorption or damage to circuitry. Popcorning of the device often can be attributed to the rapid expansion of entrapped moisture during exposure to high temperatures.
Ideally, the device should survive several reflow cycles after being exposed to factory floor conditions during normally scheduled assembly production. Diffusion of moisture into area arrays typically follows Fick's law of diffusion; however, solving the multilayer diffusion problem (diffusion through more than one surface layer, as well as the exposed ends of the substrate) requires that all material properties be known. Therefore, it usually is necessary to determine the moisture sensitivity for each type of package. Moisture desorption (bake-out requirements) needs to be measured for each device type as well. Moisture-sensitive components may require a pre-assembly bake out in addition to storage in a dry nitrogen chamber. In general, CSPs show almost complete moisture desorption following a four-hour bake out at 125°C. However, larger devices and moisture-sensitive BGAs typically require bake out at 125°C for as much as 24 hours (Figure 2).
 Figure 4. Non-wetting/small ball open. |
Setup and Quality Control: Correct setup of the equipment is important for ensuring high throughput and yield. The setup used at every stage of the PCB assembly process should be reviewed thoroughly and validated properly by domain experts. Gage studies should be performed to maintain consistency from line to line and operator to operator. Equipment and operator performance can be assessed by printing stencils onto a bare laminate before each shift, placing test components onto double-sided taped boards and using a data logger with a thermocoupled board in the reflow oven. More advanced methods can implement assembly of test boards, in-process measurement of process variables, and characterization of the placement machine with precision chrome/glass components and boards.
Training and Education: Operator training not only should focus on equipment but needs to be extended to include assembly process and general surface-mount issues. Familiarity with the overall process can help the operators understand what happens down line from their operation. Mistakes and improper education can affect subsequent operations, and the operators must understand the result. Human error can be minimized by combining training, use of proper equipment and tools, and profit-oriented attitude. Operators often assume that the end product can be reworked if they do not assemble the product properly the first time; this assumption can be costly.
Methods
Solder Deposition: In CSP assembly, both paste deposition and preformed solder spheres are used to create a solder interconnection between the package and the PCB. Most CSPs use a eutectic or near-eutectic Sn/Pb solder alloy. Some CSPs and BGA components may use high-melting (above 300°C) solder alloy (5/95 Sn/Pb) balls to prevent the device from collapsing during solder reflow. The eutectic BGA device spheres melt during a standard reflow process and collapse to an equilibrium state. Equilibrium is achieved with the balance between package weight and the buoyant force of molten solder surface tension. With eutectic CSPs, there is a sufficient amount of solder in the component ball to provide interconnection; however, coplanarity of the device becomes critical to ensure that each bump forms a proper joint.
 Figure 5. Ball height distribution. |
The most common method for solder deposition in CSP/BGA assembly is solder paste stencil-printing. In this process, solder paste is deposited onto the attachment pads of the board through corresponding holes made in a metal foil. For fine-pitch CSPs, the printing process becomes critical because there is insufficient room to elongate the solder stencil apertures. Printing circular features greatly reduces the amount of paste transferred through the aperture. For 0.5-mm-pitch CSPs, it is not uncommon to achieve a print efficiency of less than 60 percent. Aperture size and stencil thickness need to be adjusted properly to ensure the highest transfer ratio (paste deposited vs. aperture volume). In general, the apertures should be oversized slightly compared to the attachment pad geometry to increase the solder deposit volume and transfer ratio. However, this may lead to an increase in solder ball and satellite formation. Nitrogen may help counteract the tendency of the paste to form solder balls during paste overprinting.
Fluxing: Since it is possible to attach collapsible (eutectic) CSP/BGAs without solder paste, attachment methods may include flux deposition. Fluxing for CSPs can be achieved by dipping the component into a flux film deposit, or through dispensing, spraying and brush methods. In order to minimize the flux residue left on the PCB following reflow, methods that deposit flux only in the needed areas should be considered. Dipping commonly is used to flux the component balls. In this method, the device ball planarity must be considered when specifying the dip depth. The dip depth must be at least one mil (0.0254 mm) larger than the ball coplanarity to ensure each bump is fluxed. The flux cleans oxides from the surfaces during the reflow operation.
 Figure 6. CSP device substrate warpage measurement. |
Fluxless methods rely on oxide removal prior to assembly, typically in a plasma cleaning system. In plasma systems, an impinging plasma gas bonds with the oxygen molecules on the surface of the sample, which are removed to leave a clean exposed surface. However, the solder paste and/or flux is used to retain the component in place during the assembly and transportation of the PCBs. The tackiness of the flux/paste required will depend on the assembly process used. In-line automated assembly will require less retention force than manual batch assembly. Additionally, placement equipment using table movement rather than head movement will require much larger retention forces because of high accelerations imposed on the PCB and component.
When a flux-only method is used for CSP assembly or rework operations, it is critical to ensure that both the bump coplanarity and warpage of the assembly at reflow temperature are fully understood. The combination of variation in solder ball volume and warpage of both the package and substrate may lead to solder joint opens. If a package has a small ball and the device has significant warpage during the reflow, there may not be sufficient solder volume to form a proper joint during the bump collapse (Figure 3).
In many cases, the addition of solder paste will help minimize the small ball open because the reflowed paste can help bridge the gap between the component bump and the PCB attachment pad. In addition, a flux-only process can result in a marginal or cold solder joint if the flux is applied in too low a volume. In the case of high-bump coplanarity, the flux may not coat the shortest bump tip sufficiently and may be unable to remove all the oxides during reflow. If incomplete fluxing occurs, a complete metallurgical bond may not form. Marginal/weak joints result in early failure during thermal cycle testing. Figure 4 shows a device failure at the component ball to PCB pad interface because of poor wetting. This device was assembled using a 2.5-mil (0.0635-mm) thick flux film. To understand the effect of bump coplanarity on assembly/joint formation, experiments were performed to determine the level or bump coplanarity and package warpage that would lead to open solder joints. During the experimentation, flux depth was varied from 2.0 to 4.5 mils (0.05 to 0.114 mm) in thickness.
 Figure 7. Assembly reflown on through-hole. |
The device coplanarity was measured for samples, as shown in the bump height distribution of Figure 5. The package warpage was measured by several techniques, including moirè, laser profilometery and interferometers.1
Figure 5 is a histogram of measured ball height for a 0.8-mm pitch CSP. Sample size is 3024 with a mean height of 15.2 mils (0.386 mm) and one standard deviation of 0.75 mils (0.02 mm). A representative warpage plot for the device is shown in Figure 6. The experiment showed that, for the device studied, a flux film of less than 3.5 mils (0.09 mm) resulted in either cold joints or opens. By repeating this experiment for many device types, it was found that, in general, the ball coplanarity for a CSP should be less than the following: 3.0 mils (0.076 mm) total ball diameter variation at 3 sigma (0.5 mil or 0.0127 mm for one standard deviation) combined with a reflow temperature package warpage of 2 mils (0.05 mm).
Reflow Soldering: The heat transfer mechanisms used in the mass reflow soldering process include convection, radiation (using infrared sources) and condensation (vapor phase). The most popular method of reflowing solder is based on forced convection or IR radiation. Some other methods of solder reflow are vapor phase, laser and hot bar. In addition to mass reflow soldering, PCBs often are subjected to a wave-soldering operation. In wave-solder applications, the PCB is passed over a molten wave of solder where the solder is attracted to all wettable surfaces, including attachment pads, component leads and vias. When CSP/BGAs are populated onto boards with mixed technology, special process concerns arise. High I/O area arrays may require a significant number of vias on the PCB. Because both heat and solder can be wicked into the via, special precautions must be imposed when subjecting a PCB populated with BGAs to a back-side wave pass. Wave temperature must be controlled carefully to prevent the top-side solder joints from secondary reflow. The higher the via density, the more heat transfer occurs, and thus more temperature control performed. Taping the bottom-side via area with a polyimide film or using peelable temporary masks will minimize top-side reflow and solder being wicked into the via. Additionally, the top-side via pad should be covered with solder mask to prevent the solder ball from misplacement or wicking into the via (Figure 7).
 Table 1 |
Uniformity of temperature across the PCB and within a component is a primary goal of any reflow system. For area array devices, a temperature gradient of 10°C or less should be maintained to prevent warpage of the package and to ensure that all joints reflow properly. For small CSPs, infrared reflow systems are sufficient to maintain less than a 10°C gradient. However, IR reflow of BGAs have much larger temperature gradients across the PCB and package because of color differences, surface emmisivity of the devices and shadow effects. Cold joints can form if a very large temperature gradient occurs. Warpage is a major concern for BGA reflow as well. Preferential heating, shadow effects and highly reflective surfaces can cause package warpage, bridges and opens to occur in BGAs. By contrast, forced convection reflow provides a substantially lower temperature gradient across the PCB and BGA solder joint array than infrared furnaces.
Placement: The strategies used to place components on boards can be divided into in-line, mass, sequential and simultaneous placement. In high-volume manufacturing, dedicated sequential or mass placement may be performed. In most cases, flexibility is important to accommodate new products and components. Typically, CSP assembly uses sequential component placement. Two types of placement equipment are used for sequential pick-and-place operations; the first is an X-Y gantry style, and the second is fixed-head moving-table placement machines. The overhead equipment offers high flexibility, medium placement speed, high accuracy, and minimal accelerations or movement of the PCB. In contrast, the table movement machines (usually rotary turret heads) offer high placement speeds and medium accuracy and flexibility, and impose high accelerations on the PCB.
Another important feature of the placement equipment that affects CSP assembly is the equipment vision system. A major issue is the ability of the equipment to recognize features on the board and component and accurately place the device by aligning the device bumps to the attachment pads on the PCB. Some CSPs have logos, nomenclature or other features on the array side of the device; these features may be misinterpreted as a ball location by a standard forward illuminating camera. Illumination of the package from a lower angle, namely side-lighting, may be required to prevent erroneous ball finds on CSPs with bottom-side non-ball features.
Materials
Solder Paste: The wet solder paste, after being deposited on the pads on the board, holds the components in place prior to the formation of the solder joint (by reflow soldering). The solder paste, at this stage, temporarily acts as an adhesive. Characteristics of the solder paste that are important from a process perspective include the solder powder particle size, metallurgy, slump, temperature and humidity sensitivity, solids content, type of flux residue, viscosity, and the propensity for solder-balling. No-clean eutectic (63/37 Sn/Pb) solder pastes with high metal content (approximately 90 percent by weight) are used widely in CSP/BGA assembly. The solder paste used for SMT assembly needs to be subjected to a battery of tests. These tests help to ensure the quality of the solder pastes used. The tests that need to be conducted include some specified by the IPC (as discussed in IPC-SF-818 and IPC-SP-819), while the rest are standard tests adopted by the electronics assembly industry. The tests that are used to evaluate candidate solder pastes include solder paste viscosity, solder-balling, solder paste slump, wettability, tack strength, printability, spread, copper mirror, surface insulation resistance and electrochemical migration tests.
While the basic characteristics of the solder paste can be confirmed through exhaustive testing, the choice of the particle size used in the solder powder for area array is dependent on device pitch. For the assembly of standard BGAs (1.27 mm), the stencil aperture size typically is 0.55 to 0.65 mm in diameter. A solder powder's particle size could range from Type 2 (-200/+325 mesh size) to Type 4 (-400/+500 mesh size). As the device pitch decreases, the aperture size will shrink. For 0.8- to 1.0-mm pitch, the device aperture size is typically 0.4 to 0.5 mm and requires a Type III paste. As the pitch is further reduced, a Type IV paste should be used. In assembly of 0.5-mm pitch, the aperture size may be as small as 0.25 to 0.35 mm. The ability of the solder paste to transfer successfully through the stencil apertures is influenced by several paste properties, including particle size distribution. A series of experiments were performed to determine the effect of paste type on transfer efficiency. Two pastes were compared (Types III and IV). Printing was accomplished using an automated stencil printer and solder paste deposition was measured using a solder paste inspection system. The following two stencil thicknesses were compared: 5 mils (0.127 mm) and 6 mils (0.15 mm). The aperture size varied from 10 mils (0.25 mm) to 13 mils (0.33 mm). Printing was performed on 20 panels with four devices each, by printing a single board, performing inspection, cleaning the board and reprinting (Table 1). On average, the Type IV paste gave 10 to 15-percent higher paste transfer efficiencies than the Type III. In addition, a dramatic effect was observed for the stencil thickness. Table 1 shows the best resulting combination of parameters for this experiment - Type IV, 0.17-mil apertures and 5-mil-thick stencils. Similar experiments were performed using 12 commercially available no-clean solder pastes to study the effects of aperture shape and size.
Fluxes: Because the application of flux may be appropriate for CSP assembly or rework, important flux characteristics, including viscosity, flux residue, and solids content, should be investigated. Screening tests can identify potential flux candidates and only those that meet process requirements should be selected.
 Table 2 |
Components: CSP components are available in different package configurations, including overmolded, flex carrier, rigid carrier and various wafer scale formats. The component-related dimensional parameters include component lead pitch, warpage, bump coplanarity, bump location deviation (radial deviation), solder bump volume, pad size and body size. Variations in these parameters will change the characteristics of the solder joint and can result in solder joint opens or satellite solder balls (with the potential for bridging). A rigorous component-handling strategy should be adopted. Moisture-sensitive packages should be baked before actual use in assembly. The solder bump metallurgy of the BGAs typically is either collapsible with eutectic (or near eutectic) composition or non-collapsible with high-lead (Sn/Pb 10/90) composition. This characteristic changes the significance of each dimensional aspect. When eutectic solder bumps reach the liquidous temperature of the alloy during reflow, they collapse. At the equilibrium state, each solder joint acts like a spring and the sum of all the forces applied on the solder joints is zero. The solder joint standoff typically is less than the original solder bump height. Therefore, the variation of the solder bump height is compromised.
CSPs serve the fundamental purposes of any IC package. They provide a metallurgical interconnection between aluminum die bond pads and the solderable metallurgy of a PCB. Simultaneously, CSPs deliver a geometric rearrangement of the IC's bond pads, often resulting in a more relaxed I/O pitch compared to the die bond pads. The definition of a CSP stipulates that the package occupies no more than 1.5 times the area (footprint) of the die, the individual side geometry is no more than 1.2 times that of the corresponding chip side dimension, and the package is direct-surface mountable as opposed to wire bonded.
Typically, CSPs provide electrical connections to the PCB in array patterns, on pitches less than 1.0 mm. While the CSP seems to offer many advantages, long-term component and solder joint reliability must be understood fully. The lack of published data and limited use of CSPs to date prompt the question of package integrity. By design, the package is only slightly larger than the silicon die, thus creating a large thermal expansion mismatch between the device and the PCB laminate. From a reliability standpoint, there are only two types of CSPs - mechanically and non-mechanically decoupled devices. Many of the devices use an interconnecting ball pattern that is referred to as a chip scale grid array (CSGA).2 However, CSPs typically are classified into the following categories:
- Interposers with a flex circuit interconnect
- Interposers with rigid substrates
- Lead on chip (LOC)
- Wafer-level assembly packages
- Wafer-level processes with redistribution.
Flexible carrier devices (elastomer interposers) incorporate a flexible circuit rerouting technique to connect the die bond pads to the solder bumps of the CSGA.2 The overlay is adhered to the die face with the back of the die exposed. The sides of the die can be exposed or covered with a protective material for handling purposes. Examples of this CSP type are the Tessera Micro-BGA,3 the Chip on Flex package by General Electric, the FlexCSP by Amkor, the MicroStar by Texas Instruments and a center pad memory module CSP by Texas Instruments.4
A subset of the flexible interposer type CSPs, die mounted to a polymer substrate without an interposer, is becoming a common package. Various methods are used in the construction of these types of CSPs, but most use a polyimide flexible, metallized substrate onto which the die is attached using standard die bond epoxy. Most are wirebonded, but literature refers to flip-chip types as well. Packages of this type include Texas Instruments' wire bonded Memoryflex, PacTech's Fibre Push on Flex and Amkor's Flex BGA.
 Figure 8. Time-zero CSP component-side failure. |
Many CSPs are using rigid substrates as interposers in an attempt to push ball grid array component technology into fine-pitch/small-footprint applications. These devices typically are wirebond dies mounted to a rigid ceramic or organic BGA interposer.2 Several flip-chip die versions are being developed as well.5 Several manufacturers are pursuing development of these devices, including Matsushita's Land Grid Array (LGA), Motorola's SLICC (slightly larger integrated circuit carrier) and Amkor Anam's Chip Array.
Lead on chip (LOC) technology uses mold resin and support lead frames as package constructing materials, which allow the CSP to retain the advantages of conventional packages while reducing the size. The technology was developed to decrease the ratios of package to die area and to facilitate the mounting of large memory devices. The other advantage is that it can use dies that are center-wire bonded.4,6 Hitachi Cable's Micro Stud BGA, Amkor's ChipSOP and Texas Instruments' Lead on Chip CSP packages are examples of LOC devices.
Various types of CSPs are manufactured in a wafer format, such as Chip Scale's Micro-SMT package and Shellcase's Shell CSP, where the packaging process starts with a finished wafer. In these devices, the majority, if not all, of the packaging is done on the wafer level and finished devices are diced and shipped.
CSPs that are manufactured using a wafer-level assembly process with redistribution layers have solder bumps that are connected internally to the die surface either by columns or by a polyimide circuit redistribution routing layer.2 Many are a smaller version of the larger molded package types or are flip-chip die with multiple polyimide layers. If the device subsequently is molded, moisture handling and moisture absorption become critical issues before reflow. Examples of this type of package include Flip Chip Technologies' Ultra CSP and National Semiconductor's Micro SMD.
Many component-related parameters affect both assembly yields and reliability. Foremost is component construction. The overall material layering and resulting CTE drastically change the solder joint reliability. In general, solder joint reliability scales with CTE. As the packaging of the die decreases, the device CTE becomes approximately that of silicon (2.5 PPM/°C). Wafer-level CSPs have composite CTE values ranging from 3ppm/°C to 5ppm/°C, while laminate-based CSPs have a ball-side CTE of approximately 10ppm/°C to 15 PPM/°C. An example of the dramatic difference in resulting reliability is shown in Table 2. An experiment was performed to study the component construction vs. reliability using several packages constructed in the same outline, die size and bump pattern. Results are compared for several package types. A three-dimensional finite element model (FEM) was created for each package. The FEM included creep, nonlinear material properties and temperature-dependant solder.
 Figure 9. Weibull distribution of PCB thickness effect. Sample 1: 0.062-in. PCB (N63 = 6036, Beta = 6.14). Sample 2: 0.016-in. PCB (N63 = 11,968, Beta = 13.6). |
A 144 I/O 0.8-mm pitch CSP device (12-mm square with a 6.5-mm square die) was fabricated using a flex carrier, ceramic carrier and laminate carrier. Keeping as many of the remaining parameters constant (e.g., motherboard, pad size, pad finish, ball size), the laminate packages lasted up to 10 times longer than the flex device and 100 times longer than the ceramic device during a 20-minute, 0 to 100°C ATC test. Many other parameters - such as solder ball size, thickness of each layer in the package, pad definition and size, and material selection - similarly will increase or decrease the subsequent device fatigue lives.
Printed Circuit Boards: Boards (substrates) made of organic materials most commonly are used in area array assembly. Board-related parameters that influence the assembly yield because of variations in their dimensional parameters include fiducial deviation, warpage, mask registration, pad size and pad location deviation (radial deviation). To prevent pads from oxidation, a solderable coating is deposited on the pad surface. The commonly used pad coating materials include eutectic solder deposited through the hot-air-solder-leveling (HASL) process, organic solderability preservative (OSP), nickel/gold, nickel/palladium, silver and tin. These coatings, resulting in different pad finishes, may change the solderability of the pad and affect the solder joint's quality. For properly formed joints, a metallurgical bond forms between the solder (Sn) and pad surface (Cu or Ni). During reflow, the Sn combines with Cu or Ni to form an intermetallic layer. While brittle, the layer is extremely strong. For properly formed metallurgical bonds between Cu or Ni and Sn, the interfacial strength is sufficiently greater than the plastic flow stress of the solder. In this case, the solder will rupture or fatigue during thermally induced strains. However, many problems exist that prevent the proper metallurgical reactions to occur. These may include improper amounts of co-deposition materials in the plating baths, oxidation of the underlying pad surface, porosity in the outermost cover layer, organic contamination, solder mask residue or improper fluxing. This problem often will lead to poor adhesion of the solder ball to the attachment pad. This can result in a very low ball-attachment yield, missing solder bumps, time zero joint failures (including de-wetting) or weak interfacial strength. In the case of weak interfacial strength, the plastic flow stress of the solder is higher than the interfacial strength, and small thermally or mechanically induced strains will cause the solder ball to detach from the pad surface (Figure 8). This can be common with the Ni/Au attachment pad metallurgy. Assembly of approximately 2 million solder joints (BGA and CSP) during this research led to more than 50 time-zero failures on packages. However, packages used in this work were a mixture of commercially available devices, pre-production parts and daisy-chained packages. Therefore, these packages may not fully represent true production CSP devices.
The time-zero failure often associated with Ni/Au pads can be difficult to detect because the solder ball appears to be attached firmly to the pad. In fact, the ball shear strength required to remove a solder ball with a marginal solder attachment may have an equally high peak shear strength when compared to a good joint. A complete load-displacement shear curve can be obtained by a ball shear test in order to evaluate the ball/pad interface. The time-zero solder failure is not caused by the same mechanism as joints that embrittle with exposure to elevated temperature. In the latter case, the joint degrades well after assembly and only after exposure to elevated temperatures (>100°C). Many theories have emerged as to the origins of the high temperature degradation.7-11 It is critical to determine the source of the failure, because poor pad coating can result in solderability problems.
The attachment pad geometry can be defined by its pattern (pad defined) or by the solder mask opening (solder mask defined). The thickness of the board and the materials used in each layer will change the overall stiffness of the board, potentially influencing its warpage or sagging during the assembly process.
Many PCB parameters affect reliability of the CSP assembly. Of the various parameters, the board thickness, pad size, pad definition and attachment pad metallurgy are the most influential. A drastic increase in CSP solder joint fatigue lives can be realized by using a thin PCB. When comparing the reliability of CSPs assembled onto 0.062-inch (1.575-mm) PCBs vs. assemblies on 0.016-inch (0.4-mm) thick PCBs, there is as much as a two times difference in fatigue lives (Figure 9). The data in Figure 9 is for a 160 I/O 0.8-mm pitch laminate carrier CSP assembled onto tetrafunctional FR4 PCBs. The data was generated using a 0 to 100°C ATC test with five-minute ramp and five-minute dwell times. Event detection, electrical mapping, dye penetration and cross sectioning methods were used to identify failures. The assembly process for the devices included the following: solder paste printing using a 5.0-mil (0.127-mm) thick stencil, placement by an overhead gantry pick-and-place machine and reflow in a nitrogen (less than 50 PPM O2) convection reflow oven.
Another equally important PCB parameter that can influence assembly and reliability is the attachment pad size. There is a direct tradeoff between yields and reliability when changing pad size. Large attachment pads lead to larger ball collapse and can accommodate a much larger ball coplanarity and package warpage. In addition, the placement, self-centering of the device and stencil-printing are more robust for large pads. However, that larger pad reduces the effective standoff height for the solder joints. The shear strain imposed on a solder joint is related to the shear angle that the joint is forced to undergo during thermal excursions. A mismatch in the device and motherboard CTE cause thermally induced strains in the solder joints.
The farther away the package is from the board surface, the smaller the shear angle for the same thermal displacement. IBM's column grid array is an extreme attempt to separate the package from the board. Smaller attachment pads cause a slight increase in solder joint standoff height. A reduction in the attachment pad size from 16 mils (0.4 mm) to 12 mils (0.3 mm) showed a 25-percent improvement in solder-joint fatigue life of a flex-based 0.8-mm pitch 180 I/O CSP (Figure 10). Shown in the plot of Figure 10 is the failure data for devices assembled onto a 0.062-inch (1.58-mm) thick PCB with Cu OSP pads. The testing was performed in a -40 to 125°C ATC. The cycle was 60 minutes with 15-minute ramp and dwell times. Event detection was used to monitor first failure.
It is possible, however, to make the pads small enough to reduce the joint robustness. In the case of a very small pad, the failure location will shift from the component side toward the board side because of a greatly reduced solder joint area. Figure 11 depicts a CSP soldered to a 6-mil attachment pad that failed at less than 500 cycles at 0 to 100°C. Note that the failure location is at the PCB side.
Attachment pad design is equally important when considering assembly tradeoffs. Pad definition and mask- vs. pad-defined geometry will change the joint shape and stress concentrations within the solder. Mask-defined geometry increases the chance of solder-mask residue on the pad surface. At the solder-to-mask-corner interface, there is a drastic increase in the stress concentration, which leads to crack initiation. Fatigue cracks generally start from the mask corner in a mask-defined geometry.
Another pad design issue is the use of a via-in-pad structure (Figure 12). Assembly onto a microvia is becoming a popular alternative to fine-line routing. Via-in-pad technology reduces or eliminates traces routed between attachment pads, allowing for a more relaxed solder mask tolerance, reduction of the possibility of exposed conductors and larger assembly pads. However, voids often form within the solder joint over the via structure.
In an extreme case, the void may reduce the mechanical robustness of the assembly. Filling the via with solder before assembly, or using plated and filled vias may eliminate this problem. Many independent theories on the presence and formation of voids exist. Most agree that voids form during the metal oxide reduction and flux outgassing stages of reflow.12-15 Yet, voids can be formed by entrapped air, mask residue and other debris as well as contamination of the attachment pads by organic materials, such as fingerprints.16
Machines and Tooling
The standard surface-mount PCB assembly process sequence is sufficient for the assembly of CSP/BGAs. This sequence includes solder paste deposition, component placement and reflow soldering. Therefore, the equipment considered in this research includes the stencil printer, the component placement machine and the reflow oven. Also, tooling was designed and made to help achieve the desired process parameters and to facilitate the assembly process.
Stencil: Printed-solder-paste volume is an important process variable. It has a tremendous impact on assembly yield. Insufficient solder paste volume may result in solder opens, while excessive solder paste volume increases the chances of bridging. Printed-paste volume is determined by several parameters. Stencil design (which includes such aspects as aperture condition, shape, size, and spacing; tapered edges; thickness and fiducial deviation) has a significant influence on the printed paste volume. Depending upon the stencil-manufacturing process (laser-cut or chemically etched apertures), the difference in the aperture wall roughness might be substantial. In order to achieve better solder paste transfer, aperture design with tapered edges should be used.
Aperture shape and size typically are dependent upon the pad design. However, overprinting (where the aperture size is larger than the pad size) is not unusual when a substantial amount of paste needs to be deposited on the pad (for example, in the case of high-lead BGAs). Overprinting often is needed for fine-pitch CSPs to compensate for low-volume transfer efficiencies found in 0.5-mm-pitch CSP assembly. The aperture could be enlarged proportionally to the corresponding pad or asymmetrically (i.e., oblong apertures vs. circular pads). When overprinting is done, the spacing between adjacent apertures is reduced (compared to that between pads) and the chance of solder balling and bridging during reflow increases. Another way to increase the solder paste volume is to increase the thickness of the stencil. It is difficult to print paste using a thicker stencil with small aperture sizes, however, because of the decreased aspect ratio (aperture area divided by aperture wall area).
Stencil Printer: The process parameters studied in the stencil printing process included the squeegee type and hardness, print speed, print pressure and the print gap. The objective of stencil printer setup is to ensure both a clean sweep on the stencil surface and a repeatable solder paste deposition process. If a polyurethane squeegee is used, squeegee hardness levels between 80 to 95 on the Shore A scale could produce appropriate and repeatable solder deposits. Print parameters, such as the print speed, print pressure and the print gap, can be adjusted to accommodate the different solder paste rheologies. The setup of the printer must be reviewed and verified by domain experts.
 Figure 11. PCB-side failure of CSP with 6-mil pad. |
Placement Machine: The throughput, accuracy and repeatability obtained from a component placement machine are a function of its design and intended application. The placement machine is usually the most expensive piece of equipment in the assembly line and its cost is proportional to the machine's features, accuracy and repeatability. The required production rate, the pitch and size of the components to be placed, and the packaging format are some of the factors that need to be considered in selecting a component placement machine. The choice of a placement machine and its capabilities is application-dependent. Placement accuracy can be defined as the deviation of the center of any component lead from the center of the corresponding circuit pad. Because of the finite resolution capability of the placement machine, the target viewed by the machine is not often the actual target. Instead, the machine's target is the point of resolution nearest to the actual target and therefore placement deviation occurs. When the distribution of actual locations is established, the accuracy is the distance from the modal point of this distribution to the machine target. The repeatability is the distance from the modal point of the distribution to the point of the maximum deviation. Statistically, repeatability can be expressed as one-half the total range of the distribution. The accuracy of the placement machine is the net effect of program accuracy, component delivery, head positioning accuracy and repeatability, and vision system capabilities. Because area array devices usually have a coarser pitch and larger ball size, the placement of BGAs does not require a comparable level of accuracy in placement compared with fine-pitch SMT devices. These CSP and BGA packages can be centered mechanically during the placement operation, unlike ultra-fine-pitch components that require vision-assisted centering. In addition, BGA packages exhibit tremendous self-centering capabilities during solder reflow.17
The types of feeders used and the size of the component also can influence placement accuracy. Larger tolerances at the feeder site where the component is located can result in a deviation of the center of the component from the actual pick-up location. The deviation on the theta axis can be exaggerated due to the larger component size. In addition, the accuracy of the measuring method plays an important role in the derived measurement. Ideally, the accuracy of the measuring method should be an order of magnitude higher than the accuracy being measured. Placement machine accuracy and repeatability in the X, Y and Q axes can be measured using the precision glass slugs and precision plate approach. A statistically valid test strategy can be used to verify the machine's published specifications.
 Figure 12. CSP assembly on 6-mil via in 12-mil pad. |
Carrier: During the assembly process, the board (substrate) needs to be supported properly to ensure board flatness. Typically, under-board supports are provided at each work station, but are not always available in the conveyor system. When thin or large boards are populated with components, such as CSP/BGAs, the weight of the board itself along with the weight of the components may deform the substrate in reflow and result in board sagging. This effect may shift the component from its designated location on the board after placement. Consequently, there is a large variation in solder-joint height, which increases the potential for solder-joint defects, such as bridging and opens. In general, carriers need to be designed and used for large or thin boards in order to ensure proper board flatness.
Reflow: The most popular method of reflowing solder is based on forced convection or IR radiation. Some other methods of solder reflow are vapor phase, laser and hot bar. Mesh belt and edge conveyors commonly are used in reflow ovens. Critical parameters that need to be controlled in the reflow profile are the peak reflow temperature, oxygen level, dwell time above liquidous, soak time, ramp rate, cooling rate, conveyor speed and the temperature difference across the assembly.
The ramp rate in the preheat zone needs to be in a reasonable range. If the rate is too low, the assembly might not be able to reach the required soak temperature quickly enough. On the other hand, if the rate is too high, components might be thermally shocked, which causes failure. Proper soak temperature and soak times are required to evaporate solvents and to activate flux in the paste. The soak time has a significant influence on the temperature difference among components. The longer the small components are kept at a fixed temperature level, the better the chance that the large components can reach the same temperature level. The solder paste must be elevated to a temperature that generally is 20 to 50 degrees greater than its melting point. Moreover, high reflow temperature promotes intermetallic growth and results in brittle solder joints. Typically, the dwell time above liquidous is about 50 to 70 seconds. Long dwell time may result in de-wetting and re-oxidation of solder joints while short dwell time can lead to non-wetting.
Reliability Results
While there are dozens, if not hundreds, of factors that affect CSP assembly yields and solder joint reliability, a few parameters prove most critical. The largest difference in CSP solder joint fatigue was found from board thickness, component device construction and attachment pad-size parameters.
Board Thickness: In general, as the board thickness and overall stiffness decrease, the resulting stress the solder joint experiences decreases. As much as a two-fold increase in fatigue life can be realized by assembling CSPs on a thin board (0.016 inch or 0.4 mm) vs. a thick board (0.062 inch or 1.57 mm).
Component Device Construction: As the effective CTE of the device is reduced, so is the expected life of the solder joints. As the packaging around the die is reduced, the mechanical and thermal properties of the package become more like that of the silicon die. Packages that have a ball side CTE that more closely matches the motherboard PCB undergo fewer thermally induced strains. Therefore, laminate-based CSPs show a longer life expectancy than flex-based and ceramic-based CSPs.
Attachment Pad Size: PCB attachment pad size selection creates a tradeoff between assembly yields and reliability. Smaller pads generally give higher reliability, while larger pads have a higher yield. Collapse of a eutectic solder ball will be limited by the wettable area of both the device and PCB pads. Surface tension of the molten solder tries to create the free energy state with the smallest value, thus a sphere. The wettable area of the attachment pads causes a truncation of the sphere. Ideally, the pads on the package and device should be the same size to allow a uniform joint shape to be formed. A 1:1 pad-to-device size ratio will give the most spherical joints. The PCB routablity is affected similarly by the pad diameter selection. Smaller pads give more circuit routing space. In general, smaller pads give a higher joint standoff and thus a better reliability compared to joints with PCB pads that are larger than the device pad.
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ANTHONY A. PRIMAVERA, process research engineer, can be contacted at Universal Instruments Corp., Kirkwood South Building, P.O. Box 825, Binghamton, NY 13902-0825; 607-779-5203; Fax: 607-779-4646; E-mail: [email protected].
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