Stacked multi-chip CSP standards
06/01/2000
A push forward
JEDEC has propelled stacked chip-scale package standardization efforts in the form of a common agreement on SRAM and flash chips in a single package.
By Daniel Chen, Steffen Hellmold, Mike Yee and Kevin Kilbuck
The miniaturization of handheld devices has certainly been a strong driver of combination memory package trends, with a proliferation of mobile phones, pagers and personal digital assistants (PDAs). The move toward shrinking packages is an undeniably powerful element in today's enabling technology base.
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In turn, many advanced packaging solutions call for innovative ways to combine high-density flash and static random-access memory (SRAM) in a small form-factor package. Besides issues of size, combo memory packages have attracted interest because these types of packages help to reduce system design and manufacturing complexities. Because micro-vias on printed circuit boards (PCBs) are charged by count, these packages move the chip wiring from the PCB to the package interposer. They also reduce the number of solder joints and balls used, which slightly improves manufacturing throughput. The logistics of provisioning two chips versus one also promotes these combination memory packages.
Ample Variations
A new packaging standard by the Joint Electronic Devices Engineering Counicil (JEDEC) addresses both packaging and pinout for multi-chip memory devices with flash and SRAM.
The package standard MO-219A describes an 8 x 8 ball matrix, 0.8-mm ball pitch, 1.7-mm thick (maximum) ball grid array (BGA) family. This BGA family allows for various body sizes, support balls and ball de-populations.
The pinout standard JESD-21C Release 11 (preliminary) has four variations that use 8-bit and 16-bit data bus NOR type flash memory with densities ranging from 1 Mbyte to 16 Mbytes. SRAM memories supported are 8-bit and 16-bit wide data bus with densities ranging from 128 Kbytes to 1 Mbyte.
 The Sharp J-SH01 cellular phone features the LRS1311A chip, which conforms to JEDEC Pinout Variation A and Package Variation BB. |
The standard is significant, in that it encompasses four variations to meet all system design requirements. Three variations use traditional SRAM chip pinouts. We call these "evolutionary" designs. One variation uses a new SRAM with a pinout similar to flash chips. We call this SRAM "revolutionary" design.
The decision to make a particular product mix for the first three (evolutionary) variations can be done at the back-end assembly stage. The fourth variation (revolutionary) needs to make the same decision at the wafer start stage. The advantage of the fourth is that SRAM and flash share the same pinout - reducing internal structure complexity and, to a minor extent, external complexity.
Package Integration as Solution
What's more, the new JEDEC standard is significant because it addresses a constant focus of so many design agendas: trade-offs between package integration and chip integration.1
Basically, this new standard is an enabling technology via package integration, which is regarded as an advantage for several reasons, including lower cost and design opportunities for flexibility to change feature sets without incurring hefty investments. While chip integration, such as system on a chip (SOC), has many advantages, it can be costly.
 Figure 1 (courtesy Mitsubishi Electronics America) An isometric view of the package described in the JEDEC standard. |
The SRAM silicon wafer fabrication process is quite different from flash, and each process technology roadmap moves at a different time and pace. The SRAM storage node formed by a J-K flip-flop has many connections, compared to a single-transistor-type storage node (1T cell) used in today's high-density, random-access flash memory.
Four-transistor cells (4T cells) plus pull-up resistors require a very special polylayer wafer process to make an SRAM with a small overall die size, low power and wide operating temperature range. They usually have two to three polysilicon layers plus one to two metal layers using 0.5-µm to 0.25-µm design rules. The next step will be to use a six-transistor cell. The process should be quite similar to a logic process, which usually has one to two polysilicon layers and three to four metal layers using 0.25-µm to 0.15-µm design rules.
In contrast, the flash cell structure uses two to three polylayers plus two to three metal layers and has a very intricate oxide layer called the gate oxide. 8-Mbit to 32-Mbit devices are being fabricated in 0.3-µm to 0.18-µm design rules. Due to high voltages used in the storage node, design rules often move at a slightly different pace than SRAM.
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Note: Pinout variations reference JEDEC JESD21C release 11 (preliminary). Package variations reference JEDEC Publication 95, MO-219A. Body size variations: AA (8 x 8 mm), AB (9 x 9 mm), BA (8 x 10 mm), BB (8 x 11 mm), BC (8 x 12 mm), BE (8 x 11 mm), BG (9 x 12 mm), BH (9 x 14 mm). For body variation AB and BE, the four outermost peripheral balls are depopulated compared to MO-219A to achieve smaller package size. TBD = To Be Decided. Please contact vendor for further information. Please check individual vendors' datasheet for application issues.
Although it has been demonstrated that a single-chip flash and SRAM is possible, these designs often must make tradeoffs in cell size and increased wafer process steps. This means increased cost on both counts. As packages approach chip size, stacking allows further reduction in the footprint. A monolithic chip would not enjoy this advantage.
In addition to cost, key factors in chip integration versus package integration are time-to-market and flexibility - perfectly demonstrated recently in the notebook PC graphics controller area. Package integration allowed both memory size flexibility and quick time to market, enabling an upper hand in the marketplace compared with integrated alternatives.
A single handset platform often is designed to fill different market segments using different memory sizes. A monolithic integrated chip would take longer to reach market and is cumbersome to change.
How JEDEC Turned the Corner
Reaching an agreement for the JEDEC standard did not occur overnight. Differences were overweighed, however, by pressure from the marketplace, which is really the underlying force that made the accord take place. Although few customers have actually dictated standards as a requirement for design-in, JEDEC members understood that they were rapidly approaching the point of no return. While each manufacturer held intellectual property and technical know-how, each also understood the need to reach interface-level standardization. In the end, the due process fostered by JEDEC allowed each member company to entrust the end result to be fair and free of bias.
As for end users, a key challenge addressed is affording customers the design flexibility they need in their end products. They will see the benefits in the form of enabling their ability to provide enhanced features and functions.
The JEDEC standard allows improved multisourcing for portable device memory. In today's under-supplied component environment, this standard is very timely and should improve system manufacturers' sourcing tasks. End users can continue to expect more wearable, thin devices with more features that are ready for use by their side.
Meanwhile, JEDEC's work in this packaging area is hardly complete. The packaging community and end user marketplace can expect to see more significant progress coming out of JEDEC in the near future. There are other work items to address - the next-generation requirements for features and functions, which are under discussion at JEDEC within its JC-42 memory committee. While standards committees often display weakness in their domination by suppliers, the JEDEC JC-42 memory committee has a good balance of representation from both suppliers and users.
References
- Daniel Chen, "Package Integration: A Viable Alternative," Advanced Packaging, February1999, p. 18.
DANIEL CHEN, director of memory engineering, can be contacted at Mitsubishi Electronics America, 1050 East Arques Ave., Sunnyvale, CA 94086; 408-774-3060; Fax: 408-730-4972; E-mail: [email protected].
STEFFEN HELLMOLD, strategic marketing manager, flash business unit, can be contacted at Fujitsu Microelectronics, 3545 North First St., San Jose, CA 95134; 408-922-9243; Fax: 408 943-1348; E-mail: [email protected].
MIKE YEE, IC technical product manager, IC memory marketing, can be contacted at Sharp Microelectronics of the Americas, 5700 NW Pacific Rim Blvd., Camas, WA 98607; 360-834-8084; Fax: 360-834-8903; E-mail: [email protected].
KEVIN KILBUCK, senior business development manager, memory business unit, can be contacted at Toshiba America Electronic Components, 9775 Toledo Way, Irvine, CA 92618; 949-455-2339; Fax: 949-859-3963; E-mail: [email protected]
How a standards agreement sends an industry message
In February, the news that JEDEC, the standards trade body, had completed work on a packaging and pinout standard, was hailed as an industry step forward. The new standard applies to multi-chip modules that include both flash silicon and SRAM, much in demand by the cellular phone market. Also, the FLASH/SRAM common standard that has been reached reflects an important turning point for the advanced packaging industry - namely, how its key players must behave in an increasingly complex environment that is not friendly to camps advocating deliberately incompatible approaches in packaging.
In packaging, as in the electronics industry as a whole, the name of the game is "coopetition," according to Bob Neal, an engineer-scientist and product manager at Agilent Technologies. Coopetition describes how traditionally competing companies now direct some of their business portions to work together, while still competing in other portions. The strategy is based on bottom line realities: It's difficult for a solo business to recoup long-term R&D investments if product life cycles are short; sharing costs with other companies can make better sense. Even in companies where coopetition is not used in the form of divisions working with those in other companies, coopetition is still a thriving concept in the area of standards.
Manufacturers are increasingly aware that their bottom lines rest on their ability to enable better capabilities in the products their customers buy. There is a heightened awareness for working cooperatively to achieve common standards. The combination flash/SRAM packaging division, resolved by the JEDEC standard, is a case in point.
The laws of the marketplace would not accommodate refusals to agree on a standard necessary to accommodate customer needs. Members of JEDEC were working for some time to find common ground in a format for multi-chip modules to incorporate both flash memory and SRAM components. Mitsubishi and Sharp, for example, were among the companies proposing stacked CSP standards back in September 1998. More companies moved in to support the specs.
Not all JEDEC standard proposals fell into the same camp. One proposal called for a package similar to existing SRAM packages, while another called for a design close to flash packages. Involved in the mix of issues were pin assign, ball layout, ball pitch and package size.
As for an answer in the form of a monolithic chip solution (system in a chip), combining memory technology with logic technology was a challenge. If it was feasible technically, it would be expensive - impracticably so for the consumer electronics base, which is a price-sensitive marketplace. JEDEC participants would need to think of solutions offering low costs.
"Standards discussions, before JEDEC, were going on in Japan, but no agreement was ever reached," according to Daniel Chen, the director of memory engineering at Mitsubishi. Chen was referring to the Electronic Industries Association of Japan (EIAJ).
Enter the Washington, D.C.-based standardization group, JEDEC, which is also a body of the Electronic Industries Alliance. Chen is a member of its board of directors.
JEDEC accomplished what the EIAJ could not: a standard packaging and pinout for multi-chip modules that include both SRAM and flash silicon. The common ground achieved by JEDEC's committee was hardly reached overnight. On separate sides of the fence were members with different approaches and proposals.
Ken McGhee, JEDEC's director of technical matters, described the atmosphere: "There was an impasse that involved two camps. When the ballots came up for a vote, the two groups voted each other down." McGhee said they realized they had an uncomfortable alternative - either strike an accord or strike out with no accord. Ballots went out again and the packaging agreement was reached.
The compromise: An 8 x 8 ball matrix on a chip scale package with four versions. Three use pinouts similar to SRAM chips. The fourth is closer to flash-chip design. Two committees, one on packaging and one on pinouts, represented a total of 205 (115 in packaging and 90 in memory).
Is the standard global? While JEDEC is a U.S.-based organization with headquarters in Washington, D.C., its membership is globally based and globally focused. "The fact that our economy is leaning toward globalization is reflected in standardization," said McGhee. "The lines have blurred."
JEDEC's membership is international, and each committee member is all too aware that standards must have a global focus. In 1997, JEDEC began holding meetings in Taiwan and Canada in a bid to alleviate concerns that, even as a U.S.-based body, its scope would nevertheless be broadly based. Of course, the Internet tsunami has also helped JEDEC. "Our standards are free on the Web. Another global boost to our exposure is that the Web enables instant access to our information," said McGhee.
Information covering the standard is available from JEDEC (the package size drawing number is MO-219, the package size is JEP-95 and the pinout is to be included in JESD-21C). For further details, visit www.jedec.org.
Nancy Cohen, Contributing Writer
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