In the News

05/01/2000

Philips launches Sea-of-IP

SUNNYVALE, CALIF.-Capitalizing on advanced intellectual property (IP) delivery and rapid silicon prototyping tools (two of the major dividends that resulted from its recent acquisition of VLSI Technology), Philips Semiconductors has launched a design methodology that will allow the vast pool of IP to be used quickly and effectively. The Sea-of-IP design methodology is a new and reportedly efficient way of creating the complex, processor-driven chips. These new system-on-chip (SOC) solutions are expected to be at the heart of next-generation high-volume consumer electronics products, such as advanced set-top-boxes, home networking and 3G mobile phones.

The Sea-of-IP approach addresses the conflicting requirements of increasing system complexity and the need for quick time-to-market by elevating integrated circuit (IC) design to a system-level design process in which fully tested IP blocks are plugged into pre-defined system architectures to create SOC solutions. This design methodology capitalizes on Philips Semiconductors' CoReUse standards and guidelines to generate high-quality reuseable IP, and leverages the former VLSI Technology's HDL-i IP delivery and Velocity Rapid Silicon Prototyping tools.

"The Sea-of-IP design methodology represents a convergence between ASICs, ASSPs, CSICs and CSSPs, with all four types of IC now being designed using the same reusable IP based approach," said Theo Claasen, chief technology officer for Philips. "In addition to having the reusable IP, you must also have IP delivery and silicon prototyping tools that put it manageably in the hands of IC designers, advanced semiconductor processes in which to manufacture the resultant system-on-chip solutions in high volume, and attractive pricing."

The IP library for the Sea-of-IP design methodology comprises more than 250 IP cores for functions such as media processing (audio and video), control processing, digital signal processor (DSP), connectivity, networking and security/encryption, plus analog/mixed-signal functions. It also includes cores for the company's TriMedia processor family and R.E.A.L. DSP family, as well as MIPS and ARM RISC central processing units, 80C1 microcontrollers, and Oak and PALM DSP cores.

As a result, designers can access processing power needed to meet a wide range of system performance and power consumption requirements. The IP library is complemented by memory generators for static random access memory and read only memory, with similar generators for non-volatile memory, dynamic random access memory; special-function memory modules will soon be added. The library complies with CoReUse standards and guidelines for IP generation, so each IP block is either inherently compliant or is wrapped in a CoReUse compliant shell. This helps ensure the compatibility needed to allow simple mixing and matching of IP blocks.

"In the future, IP will become the essential condition for doing global business," said Classen. "OEMs will no longer choose their silicon suppliers purely on the grounds of process technologies, design flows and manufacturing capability, but on how closely a silicon supplier's IP portfolio aligns with their own product roadmaps."

Philips Semiconductors now has its Nexperia silicon system platform for digital video fully defined, with similar platforms for digital communications and car infotainment systems nearing completion. The Sea-of-IP also extends to more traditional application-specific integrated circuit (ASIC) designs, allowing users to develop their own system architectures. And through its extensive use of function compilers and reconfigurable IP blocks, it retains the data-path flexibility required to fine-tune designs for optimum performance.

IP delivery is via an updated version of the former VLSI Technology's HDL-i (high-level description language integrator), which has been adopted by Philips as its preferred tool for all future IP generation and delivery systems.

The Sea-of-IP design methodology is targeted for its latest 0.18 micron CMOS process, with plans already in place to migrate it to 0.12 micron CMOS and to incorporate IP blocks for the company's advanced QUBiC3 and QUBiC4 RF BiCMOS processes.

Optical lithography creates tiny transistors

SAN JOSE, CALIF. - Numerical Technologies Inc. (NumeriTech) has successfully fabricated the world's smallest gate-length transistors produced entirely by optical lithography. The 50-nm (0.05 micron) transistor gates were achieved using a patented phase-shifting technology and DUV 248-nanometer optical lithography. The devices were fabricated at MIT Lincoln Laboratory (Lexington, Mass.) as part of a DARPA-sponsored program on sub-100 nm fully depleted SOI CMOS.

This achievement reportedly marks the first time 248-nm lithography equipment has produced a 50-nm device. The transistors represent some of the smallest gates ever patterned by direct optical lithography. This result also demonstrates the potential for existing optical lithography tools to generate feature sizes significantly smaller than originally anticipated.

"People have been predicting the end of optical lithography for several years, saying that it can't extend beyond 100 nanometers," said Y.C. (Buno) Pati, president and CEO of NumeriTech. "The MIT Lincoln Laboratory results prove that with prudent use of phase shifting, optical lithography can be extended much further than anyone ever thought was possible."

Previous estimates have held that 157-nm lithography equipment would be required to print lines at 70 nm, and industry sources agree that 157-nm may not be available for seven to 10 years.

Intel invests $250 million in Infineon

SANTA CLARA, CALIF. - Intel Corp. has signed a definitive agreement to invest $250 million in Infineon Technologies AG in a private placement subject to certain closing conditions, including necessary regulatory review. Additionally, Infineon and Intel have agreed to cooperate in the production of DRAM memory products. As part of this agreement, the companies will share roadmaps, and Infineon will increase its manufacturing capacity for DRAM memory products, as well as support production of Direct RDRAM memory technology. Direct RDRAM technology helps improve computer system performance by providing faster memory access to meet the increasing performance requirements of today's newest generation microprocessors.

Motorola's DigitalDNA to benefit 64 universities

CANCUN, MEXICO - Motorola Inc. has extended its strategic partnership with the Ibero-American Science and Technology Education Consortium (ISTEC) through an academic license valued at $20 million. The license grants 64 Latin American, U.S. and European universities access to Motorola's family of core-based digital signal processor (DSP) technology, and expands the company's advanced DigitalDNA technologies across Latin America.

The agreement gives educators and students at member universities access to this technology, upon which students can develop total systems on chips. Motorola's DSP568xx core is designed for both DSP and microcontroller operations, making it a good mass-market solution set for low-power, general purpose applications that can be applied to the digital wireless messaging, end point telephony, industrial control and digital imaging markets.

"A broad knowledge base of state-of-the-art design practices is essential to the explosive growth in Latin America," said Gustavo Arenas, corporate vice president for Motorola and general manager of Motorola's Semiconductor Products Sector operations throughout Latin America and the Caribbean. "ISTEC is a powerful partner for us. Together, we are enabling the use of smart technology at some of the world's most prestigious engineering and technical universities."

Motorola is providing the necessary elements for students to take a design from concept to an integrated system-on-chip. ISTEC member universities will receive the DSP568xx core design, bus standard specifications and peripheral IP bus bridge, a library of peripheral modules, and a memory controller and interface modules.

In addition, Synopsys, a leader in complex integrated circuit (IC) design, announced a license of its Electronic Design Automation software to the universities that obtain access to Motorola's DSP technology.

Loctite acquires Multicore

Düsseldorf, Germany - Henkel KGaA has recently assumed ownership of Multicore Solders, the world's third largest soldering materials company. James J. Heaton of Loctite, a Henkel business unit, said, "The acquisition broadens our product offering with a line complementary to our existing range and provides a platform for future expansion into the electronics assembly market." It is expected that Loctite and Multicore will operate as distinct and separate companies and will continue to service their customers independently. However, cooperation has already begun in overlapping areas of product development and opportunities will be sought for each company to make use of the other's sales organizations.

Newsmakers-People

Pfeiffer Vacuum, Nashua, N.H., has appointed Roland Hellmer to the position of executive vice president.

Rocky Hill, Conn.-based Loctite Corp. has named James J. Heaton vice president of marketing for its electronics business unit.

Monrovia, Calif.-based Electrocube Inc. has announced new ownership and management, with Don Duquette serving as president and L. Clay Parrill as vice president and general manager.

Unitek Miyachi Corp., Monrovia, Calif., has named Mark Rodighiero vice president of its laser and systems division.

Kay Nimmo, director of research and development at Soldertec, was awarded Best International Paper and a Special Recognition Award for Research and Training on Lead-free Alternatives at IPCWorks '99.

Carol A. Latham, president and chief executive officer of Thermagon Inc., Cleveland, Ohio, was inducted into the Ohio Women's Hall of Fame.

Santa Clara, Calif.-based ChipPAC Inc. has appointed Bruce Stromstad to vice president of manufacturing processes and planning.

Newsmakers-Companies

MRSI Group, Chelmsford, Mass., will open a new corporate facility in Tewksbury, Mass., in September.

Semiconductor Equipment Corporation, Moorpark, Calif., is celebrating its 25th year in business as a designer and manufacturer of assembly and handling equipment for semiconductor and hybrid devices.

Precise Technology Inc., North Versailles, Pa., has announced that its molding facilities in Massachusetts, Precise Holden and Precise South Grafton, have received ISO-9002 quality registration.

Trace Laboratories-Central, Palatine, Ill., has formed a cooperative relationship with TUV Rheinland of North America Inc. to provide a wide range of testing and certification services to manufacturers.

Indium Corporation of America, Utica, N.Y., was recognized for its efforts in the electronics assembly materials industry by Belgian-based Electronics Manufacturing International magazine.

Aegis Industrial Software Corp. has opened a new, larger headquarters at 980 Harvest Drive, Suite 230, Blue Bell, PA 19422.

Japan Fine Coatings, a 50/50 joint venture between DSM Desotech (Elgin, Ill.) and JSR (Tokyo), has begun construction of a new plant for the manufacture of high-performance UV-curable materials in Tsukaba, Japan.