Test methodologies and systems require paradigm shift
02/01/2000
KEITH L. BARNES
Leading semiconductor manufacturers argue that the cost of test is the single greatest contributor to the total cost of bringing an integrated circuit (IC) to market. If this is true, this plays a critical role in the success and profitability of newly emerging system-on-chip (SOC) technology. Semiconductor manufacturers hope to keep the cost of test and time-to-market for SOC development in line with today`s application-specific integrated circuit (ASIC) devices; this may prove to be a daunting task given the complexity of SOC designs and the magnitude of challenges manufacturers already face at virtually every level of development. However, even these challenges can be manageable if the very nature of test methodology changes and adapts to the new design and development approaches being forged by system level integration technology.
SOC devices integrate individual cells of logic, analog and some memory functions into a seamless functional system. This high level of functionality onto a single piece of silicon, which often includes embedded programmable elements (such as digital signal processors, microcontrollers and multiple cores), is complex and time-consuming. And enhanced millennium versions, which may comprise three of every five ICs produced, are planned for even more intricate integration of capabilities, such as on-chip Rambus, and for a completely autonomous operation that may eliminate many of today`s plug-in peripherals.
Even more intimidating than the intricacy of the SOC designs themselves are the myriad of challenges semiconductor manufacturers face in developing them. These challenges include new manufacturing methods, new material processes, testability, time-to-market, reliability and cost issues. Of these, testing SOCs successfully, and the time and cost to do so, may prove to be the greatest challenges to surmount.
Today`s ASIC test methods simply do not apply readily to SOC technology. With multiple functions, it is difficult to test a system that has no single encompassing technical specification across the spectrum of the device. Integration of various multiple functions, as well as transitions between software and hardware, pose their own set of validation problems. Test complexity aside, test time and cost are still paramount issues. Some semiconductor manufacturers report that test development and debug today comprise up to 50 percent of the total IC development time; this is for ASIC development alone. For the SOC to be successful, and for manufacturers to continue to reduce costs and show a profit, validation and final test for these products will need new testing approaches and possibly new types of systems.
According to Patrick Gelsinger, vice president and general manager of Intel`s desktop products group, at the 1999 International Test Conference, "Test has got to change." The cost of production test per transistor has remained flat or has increased during the past 20 years, while the cost of building ICs continues to decrease. Gelsinger further stated that the cost of test is "out of control" and that testers must adapt to the same dynamics that drive the development of complex microprocessors. That is, it is necessary to adapt a "Moore`s Law for test costs" for future IC devices if semiconductor manufacturers are to realize the same success and profitability as they have with current ASIC designs.
As SOC technologies move into the mainstream and development economies are sought in test, the place to look may be in new methods and systems that focus on full validation in the back end of the product cycle. If it is possible to functionally test ICs with new design-for-test (DFT) methods before first silicon, combined with IC validation systems at first silicon, new testing economies may be realized for both ASIC and SOC devices.
By using simpler, low-cost DFT software and engineering validation systems, SOC products could be fully validated, characterized and then shipped after the first successfully validated prototype, vastly reducing or potentially eliminating the final test phase with an automated test equipment (ATE) system. The throughput power of the ATE system would be refocused for rooting out failures in materials processing. With this simpler mission, ATEs could shrink in complexity and cost, further reducing the cost of test and, ultimately, the cost of IC development.
This new paradigm for test methodologies and systems would afford the industry the opportunity to lower test and other manufacturing costs. It would also allow semiconductor manufacturers an opportunity to design and build advanced SOC technology cost-effectively, with similar time-to-market achievements, as successful ASIC devices being produced today.
KEITH L. BARNES, president and CEO, can be contacted at Integrated Measurement Systems Inc. (IMS), 9525 SW Gemini Drive, Beaverton, OR 97008; 503-626-5368; E-mail: [email protected].