Die placement
02/01/2000
Die placement
Step 2
With the ongoing demand to reduce product size while producing more functionality, die placement continues to be an important step in the advanced package assembly process. Crucial die placement considerations include the die presentation and metrics, material properties of the flux, force of placement, and substrate imaging capabilities.
JACQUES CODERRE
ROBERT PETER
The placement of semiconductor devices onto a substrate or a board is generally referred to in the industry as the die placement, die attach or die bonding operation. Although the basic premise is the same, the method of attaching the die to the substrate, the process and the equipment configuration vary greatly. The variations depend on the application, the assembly itself and, most of all, the method used to interconnect the chip within the package.
The packaging for semiconductors must support four basic functions: power distribution, signal distribution, heat distribution and environmental protection.1 As the requirements for these functions evolve, so do the assembly processes. With today`s trend toward increased functionality, as well as the ubiquitous "smaller, faster, cheaper" technology drivers, die assembly must perform several tasks: It must not only support the traditional mechanical functions, but it also should minimize the overall assembly size, minimize electrical noise, permit maximum electrical performance and ensure optimum heat dissipation.
The most widely used method of interconnection is wire bonding. In this method, a gold or aluminum wire is bonded to the die circuitry and ball bonded to the substrate. This method has served the industry well - more than 95 percent of all semiconductors today are assembled using this technique. Another technique, however, is marked for future exponential growth: the flip chip interconnection approach. In this process, the bumped device is mounted to the substrate active side down. The technique is called "flip chip" because the active circuitry faces down instead of up, as in the case of wire bonded devices. Die placement processes, pertaining to both wire bond and flip chip interconnection techniques, are discussed in this review.
General Die Placement Issues
In general terms, a die placement cycle consists of the following steps:
1. Pattern recognition of the substrate using global or local fiducials (or the circuit itself);
2. Picking of the die (either single or gang picking);
3. Imaging and theta correction;
4. Placement of the die.
Whatever die placement techniques are used, die presentation and substrate handling issues are shared by all. Die may be presented for placement in various ways, such as in wafers, waffle packs, and tape and reel. Choosing the optimum die-feeding scheme depends on various factors, such as upstream processes, wafer yields, die sizes and die sorting requirements. A wafer-handling scheme is well-suited for applications where the wafer yield is high and the devices are small. On the other hand, tape and reel presentation may be appropriate for applications where the devices are larger and the wafer yield is low. In direct chip attach applications, for example, die are sometimes processed before the die placement operation. In this case, the die will have been sorted before the die bonding operation, and will be presented for placement via either waffle packs or tape and reel.
In the case of wafer processing, wafers are received after dicing on a film frame. Cassettes of 25 wafers are fed to the machine, and one wafer is indexed into the machine for placement. Frames are stretched to permit optimum mapping and picking. To pick a device from the frame, an ejector pin pushes the die off the frame while the pick head of the machine lifts the die (Figure 1).
Substrates vary widely in the industry. By far, most semiconductors today are bonded to metallic lead frames that subsequently become plastic packages, such as thin quad flat packs. Other materials include rigid board materials, such as FR-4 and BT, ceramics, and polyimide flex circuits. Devices are sometimes placed in metal housings, as in the case of optoelectronic devices. Silicon itself may be the substrate in so-called silicon-on-silicon applications and other three-dimensional packaging schemes where die are stacked.
The lighting scheme and camera resolution are critical and application- specific. For flex circuit assembly, for example, blue lighting provides supe- rior imaging resolution over the trad tional 660 nm red light. In the case of co-fired ceramics, the use of polarized light provides a better contrast between the alumina ceramic and the circuit metallurgy.
Die Placement and Wire Bonding
When placing a wire-bonded device in a package, such as a thin small-outline package, ball grid array or chip scale package (CSP), the die is attached to the substrate by using an adhesive. Epoxy-based die attach materials are the most widely used. The organic adhesives are typically filled with silver filler particles to meet thermal and electrical conductivity requirements of the package. The silver-based adhesive may be screened or dispensed onto the substrate depending on the application. The amount of material required varies with the die size. In general, the amount is controlled to preclude any material climbing onto the active side of the die, and to regulate the thickness of the adhesive otherwise known as the bond line.
The most common approach used for component assembly is to perform the dispensing and placement operations on one machine that is commonly referred to as a die bonder. For high-volume, direct chip attach applications, such as chip on board, chip on ceramic or multi-chip modules, upstream dispensers or screeners followed by dedicated placement machines may provide optimum throughputs.
As we look toward the future, high-density wire bond packages are forecasted, for which the pitch between bond pads will be reduced to below 50 µm.2 For such fine-pitch applications, high placement accuracy is needed to precisely align the die and substrate bonding pads. Other novel packaging approaches, such as CSPs, also drive unique variants to the standard die placement process by adding heat and dwell times to the placement cycle.
Die Placement and Flip Chip
IBM introduced the flip chip process in 1964 when a new bumped die was used in a ceramic-based package. It has been used captively since then by companies like IBM and Delphi Electronics. Merchant applications have emerged during the past five years as pin count, electrical performance and miniaturization requirements have stressed the limits of the conventional wire bond process. Infrastructure issues, such as the cost and availability of wafer bumping and microvia substrates, are being resolved and 40 to 50 percent annual growth is projected.
The actual interconnection between a solder-bumped die and a given substrate is ensured by reflowing the die/substrate assembly through a nitrogen atmosphere oven. The temperature profile depends on the composition of the solder joint. The most common alloys are the high melting 95-97%Pb/5-3%Sn and the lower melting eutectic alloy 63%Sn/37%Pb. In such processes, there is no need for die attach materials. A fluxing operation, on the other hand, is required to remove the metallic oxides on the surface of the substrate, thereby ensuring good wetting. A typical flip chip line, including capacitor placement, is shown in Figure 2.
Important die placement considerations include the die presentation and metrics (size, bump diameter and pitch), material properties of the flux (viscosity, tackiness, wetting and amount of residues after reflow), force of placement and substrate imaging capabilities. The placement accuracy needed is dependent on the bump pitch and diameter. Because of the self-realignment properties of flip chip, tight pitch applications are possible. The Semiconductor Industry Association (SIA) in its technology roadmap predicts that bump pitches below 100 µm will come of age in the second half of the next decade.2 To place such fine pitch devices, high accuracy linear motor placement machines must be used coupled with high-resolution vision systems and high throughput capabilities.
There are several approaches to fluxing. The first approach is to dispense the flux, flood the chip site with the flux and then place the chip down. A dipping method may also be used (Figure 3), which consists of dipping the die into a film of flux and then placing the chip onto the substrate. Introducing a low-solvent flux onto a rotating drum generates the film, and doctor blades ensure a uniform thickness. The film thickness requirements are dependent on the material properties, bump height and the bump-to-bump height variation. The presence of post-reflow residues is of major concern because of the subsequent interaction with the underfill.
Even though flip chip has been in use for more than 30 years, it is still con- sidered an emerging technology. As such, new materials and processes are continuously being introduced to the marketplace. Underfill materials, for example, are being introduced that will combine the fluxing and underfill operation into one. Although limited in use because of reliability constraints, these flux encapsulant materials, as they are appropriately called, promise a significant cost improvement over existing underfill processes. Because these materials must be delivered before die placement, they will significantly change the flip chip placement operation.3 In the most distant future, wafer scale packaging promises to further simplify the assembly process by moving the underfill process to the wafer level. This will, however, create a whole new set of challenges to die placement.
Acknowledgments
The authors thank Joe Murphy, Dan Rude and Jennifer Rivkin for their assistance in preparing this article.
References
1. R. Tummalla. et al, "Microelectronics Packaging Handbook: Semiconductor Packaging," Volume 2, Chapter 8, 2nd edition, 1997.
2. SIA Technology Roadmap, www.sia.org.
3. J. Coderre, "Flux Encapsulants - Dispense and Place," unpublished paper, to be presented at Apex 2000 conference, Long Beach, Calif. March 14-16, 2000.
JACQUES CODERRE, advanced semiconductor assembly product manager, can be contacted at Universal Instruments Corp., P.O. Box 825, Binghamton, NY 13902-0825; 607-779-4362; Fax: 607-771-8116; E-mail: [email protected]. ROBERT PETER, product manager, can be contacted at Alphasem AG, Andhauserstrasse 64, CH-8572 Berg/TG, Switzerland; 41-71-637-6363; Fax: 41-71-637-6364; E-mail: [email protected].
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Figure 2. Typical flip chip line.
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Figure 3. Rotary thin film applicator.