Millenium Prediction: A Package for All Occasions
01/01/2000
A new year brings emerging markets and new trends.
RICHARD BRANCATO
president
ASAT Inc.
Looking for the perfect package? For the semiconductor manufacturer, selecting the optimal packaging solution can be tough. To make the "right" choice, it is important to comprehend both the technical and business requirements of their product.
For the longest time, the focus was on the chip - making it smaller, faster, more powerful and more eYcient while simultaneously reducing cost and improving reliability. Back in those days, you could not get into much trouble because packaging was simple. Semiconductor manufacturers simply designed the integrated circuits (ICs) or discretes, packaged them in different sizes and shapes, then tested and sold them.1 This was prior to the introduction of advanced IC packages. Today, it is a different story because there are as many IC packages as IC designs. And now there are thermal and electrical considerations. Manufacturers must have a thorough knowledge of IC packaging and all of the options before deciding on a package type for their products.
IC manufacturers who wish to take advantage of the new paradigm in packaging must be prepared to confront the accompanying challenges. This paradigm requires a substantial investment in new design software and test tools and a major revamping of test methodologies and processes. In support of these changes, semiconductor companies will have to recruit experienced packaging engineers and develop skilled design and test organizations. Companies not prepared to make substantial commitments should consider partnering with a trusted subcontractor possessing the skills and capabilities necessary to ensure success.
Technology Roadmap
Semiconductor makers and packaging engineers are confronting a new set of challenges as ICs become faster, smaller and more power hungry. Today`s engineers can design the most advanced electronic products imaginable, but what is the cost to produce them? Keeping pace with the latest technological advances demands implementing massive changes in package design and routing practices (Figure 1).
New surface mounted packages have become popular for various reasons, not the least of which is their ability to pack more input/output (I/O) into a given area than older formats. Additionally, since they tend to operate at extremely high speeds, these packages must exhibit lower parasitics. Today`s evolving, high-density packages typically fall into the following categories:2
- Fine-pitch ball grid arrays, which are housed in extremely small chip scale packages (CSPs);
- Packages utilizing flexible substrates, which are the smallest;
- Rigid-substrate packages, which are slightly larger;
- Leadless plastic chip carriers (LPCC), which are lead frame-based packages (chip size packages typically used for lower pin counts);
- Thermally enhanced packages, which may include:
1. The exposed pad package (EPP) - e.g., thin quad flat pack (TQFP) or small-outline integrated circuit (SOIC);
2. The tape ball grid array (TBGA);
3. The LPCC.
Improved electrical and thermal characteristics are the most important benefit of today`s high-density packages. These parameters are often dramatically improved with an advanced package type.
The desirable features of high-density, fine-pitch packages are not without trade-offs. As the devices become smaller, they also become exceedingly diYcult to design, route and test (Figure 2). Therefore, device manufacturers and packaging engineers must ask the following questions for each new semiconductor design:
- How must the package be designed?
- What is the most effective way to test it?
- What performance improvements can be expected?
Another consideration in package selection concerns flexible substrates. While flexible substrates offer the highest densities and smallest sizes, they typically do not provide the same board-level reliability results as rigid substrates. To achieve success working at these densities, chip manufacturers must be prepared to invest in more complex designs as well as a highly sophisticated means of modeling both thermal and electrical parameters.
Specific Considerations for Advanced Packages
The EPP is a standard leaded package that can be soldered down. The TBGA is the highest performing plastic package available; it is offered with both single- and two-layer tapes, giving designers the flexibility to add the advantages of options, including controlled impedance, matched impedance and minimized ground-bounce shielding.
In addition, the TBGA is a preferred package choice because its structure allows multiple ground planes, multiple power planes, multiple bond rings and optimized signal routing. Thus, the materials typically used in TBGAs generate the lowest possible parasitics of any plastic package.
The highly attractive benefits of this package pose significant manufacturing challenges. Modeling is diYcult with the TBGA, so highly sophisticated tools must be used. Particularly for thermal modeling, complex software tools are required. Of course, skilled modeling expertise is a prerequisite for using these advanced tool sets.
ASAT`s proprietary LPCC is given as an example of an advanced package (Figure 3). It is a lead frame-based package typically able to accommodate up to a 50 percent reduction in package size compared to standard plastic leaded packages. Several options are available. Those with exposed die-attach pads offer dramatic improvements in thermal and electrical characteristics because the exposed pads can be used as a ground plane as well as a heat sink.
The LPCC offers the potential of becoming the most cost-effective package for high-speed, high-frequency applications in lower pin count packages. The demand for this package type is increasing at a tremendous rate, and the packages themselves will be a registered JEDEC standard within the next year.
Because of the LPCC`s unique construction, however, it is diYcult to apply standard test methods. The die-attached pad is typically soldered to the printed circuit board, and since the electrical measurements are referenced to a ground plane, accurate capacitance measurements are diYcult to obtain. Since standard electrical test measurement techniques cannot be used, new ones must be developed.
The Significance of Flip Chip
You would think that technology is invented when it is required - not the case in flip chip technology. So while flip chip packaging has been in existence for more than 30 years, it is only beginning to show promise for widespread use today.
What is a Flip Chip?3
"Flip chip" refers only to the method of attachment or interconnection; the chip is flipped to bond the active side of the chip to the next level of interconnect. No implication is made about what the chip is attached to when the term flip chip is used by itself.
Flip chip in package (FCIP) refers to the use of flip chip attachment into a package. FCIP is used in single chip packages as well as multichip modules. This is typically done when the electrical performance of wire bonded leads is inadequate, when the number of I/Os is too large for wire bonding or when there is not enough space for wire bonds to be made. This is considered to be a first-level type of interconnection (Figure 4).
Direct chip attach (DCA) refers to the direct attachment of the chip to a circuit, which is usually a printed circuit board (PCB) or a flex circuit. Flip chip on board (FCOB) is direct chip attached to a PCB. The term flip chip is often understood to mean FCOB. DCA bypasses what is called first-level interconnect, attaching a chip to a package.
A wide variety of implementations exist for flip chip packaging, although many use some form of the controlled-collapse chip connection (C4) bumping process invented by IBM. Though flip chip has been promoted as the next interconnect method for decades, its main use has been for high-performance military and microprocessor devices, while wire bonding has remained the predominant method for commodity parts.
The limitations in flip chip packaging technology have prevented its widespread adoption. For example, the infrastructure for manufacturing, testing and handling of flip chips from semiconductor vendors is not yet complete. Flip chip packaging has existed long enough for some vertically integrated companies to develop mature methods, but there is a lack of standards due to its limited adoption.
General Market Forecast
The electronics industry is estimated to be a trillion dollar market, and the semiconductor industry alone is approximately $137 billion. Electronic Trend Publications predicts that in the year 2000, the total assembly market will be $20.4 billion with the independent assembly market coming up to roughly $8.5 billion.4 Further, independent assembly is predicted to have a CAGR of 16.1 percent between 1998 to 2003 while total assembly CAGR is only 12.5 percent during that same period. The significance of these statistics is that the contract assembler`s portion of the market is getting larger, which is good news for manufacturers.
But advanced packaging people want to see the entire packaging market to know where opportunities for growth exist. In a "Packaging Trends" report from Dataquest,5 Table 1 shows worldwide IC package production, while Tables 2 and 3 show projected growth by application and semiconductor application drivers.6
Telecommunications ICs are hot, with data processing and consumer following behind. The communications IC market offers the fastest growth and highest revenue. So, which packaging types are going to be in the largest demand in the next few years? It should be no surprise that ball grid array and CSP (including flip chip) are the future for the advanced packaging industry. The other packaging types will continue to be produced, but the demand is clearly tapering off.
Trends
To focus on trends that are most significant to the lives of contract assemblers and how they impact the total assembly market, trends, such as the decline in price per lead (as price erosion is common to all manufacturing industries), were omitted.
Consolidation of the Packaging Foundry Industry
Is it a surprise that the industry is experiencing a shake-out? Some of the companies that were expected to do well have dropped out while others that have just come onto the scene have risen and done better than expected. The ultimate market will include three to four large vendors, many hot start-ups and fervent acquisition activity. There are many reasons why mergers and acquisitions are taking place. One of the more common reasons involves foundries that want to increase their customer base. This can be accomplished by offering more services, such as adding test or tying into a wafer fab.
Economics is a second common reason for the increase of mergers and acquisitions. The pricing for many packages has dropped quickly over the past year as a result of overcapacity in the industry, and everyone is trying to gain market shares to hold their volumes constant. Stronger companies will purchase weaker ones to gain economies of scale. Independent assembly houses will continue to take over more of the manufacturing process.
Since the market is in constant flux, IC manufacturers that wish to remain significant players must be prepared to continuously invest in new design software and test tools, and frequent revamping of test methodologies and processes is required.
Emerging Markets Will Drive New Package Designs
Packaging needs from emerging markets, such as portable computing devices or information appliances, will drive the new package designs. This will require an ever-expanding technology base of new processes, materials and equipment. Electrical and thermal requirements will continue to increase as devices operate at faster speeds on lower voltages. Keeping up with the technical requirements is a large challenge in itself. Smaller packages with more functionality is the trend. This will require reduced communication loops with the customers and end users to speed time-to-market.
It is no surprise that foundry capacity is shifting to leading-edge technologies. This is due to a fundamental thought process change. Now assemblers are required to design the interconnect of the system, not just the package. This results in a blurring of the lines between front and back end, chip, module and board. Designing and manufacturing packages requires knowledge of the entire electronics system, hence the commonly used terms "systems-on-a-chip" or "system in a package."
Furthermore, the computer, communications and consumer markets are converging to bring the user more portable and easy-to-use end products. Witness the Web-enabled cell phones that provide Internet access and then imagine what types of hand-held or implantable portable devices will be introduced within the next few years.
Foundry Demand Is Picking Up
Leading foundries are reporting increasing fab utilization rates. While this is not yet a widespread trend, it shows great promise for the future. The fabless demand is somewhat higher than expected both in communications and in digital consumer products. Integrated device manufacturer (IDM) companies are outsourcing to foundries, and IDMs are beginning to use the foundry strategically. Demand is being driven by mobility and systems level integration, affecting silicon design.
Summary
It is often said that the only thing constant is change; this is also true for the contract assembly market. The days of creating new standard packages are gone, and the era of packaging processes is here.6 This means that packaging is similar to the wafer fab. Electronic design automation (EDA) tools are being developed to encompass design issues for the package, board and chip, and it is the contract assemblers who are leading the development of these changes.
Some very good news: market conditions are improving. Growth drivers are no longer just personal computers - emerging markets, including wireless, are exploding. The trend for outsourcing is continuing, making contract assemblers very happy. Those who are willing to change with the times and have the ability to invest in new software, methodologies and processes will do well going into the next millennium. So whatever application you are considering, there is a package for all occasions.
References:
1. Gil Olachea, "Unearthing the Perfect IC Solution," EP&P, July 1999, p. 18.
2. Ed Combs, "Keeping Pace with Technological Changes in Package Design and Selection," Chip Scale Review, September/October 1999, p. 48.
3. John Baliga, "Flip-Chip Packaging: Prepare for the Ramp-Up," Semiconductor International, Archives, March 1998. Note: definitions of various flip-chip methodologies described in article with permission of John Baliga.
4. The Worldwide IC Packaging Market, 1998 Edition, Electronic Trends, Inc.
5. Table from Special Report by Dataquest, a Unit of GartnerGroup, "The Millennium Will Bring Many New Packaging Trends," November 1, 1999.
6. Tom Starnes, Principle Analyst, Dataquest presentation at MEPTEC, September 10, 1999.
RICHARD BRANCATO, president, can be contacted at ASAT Inc., 46335 Landing Parkway, Freemont, CA 94538; (510) 249-1230; Fax: (510) 249-9105; E-mail: [email protected].
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Figure 1. Progression of packaging types from 1970 to 2001.
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Figure 2. Interconnect complexity for advanced TBGA packages.
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Figure 3. Cross-sectional view of ASAT`s LPCC.
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Figure 4. Cross-sectional view of flip chip with overmold.
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