Low-cost High-throughput Flip Chip Processing
01/01/2000
Reliability Based on No-flow Underfills
DANIEL F. BALDWIN,
RYAN THORPE
BRIAN J. LEWIS
Flip chip assembly technology is gaining increased acceptance in the electronics industry. Annual growth rates projected through the next decade are 40 percent or higher. While flip chip technology was developed more than 30 years ago and has been in production on ceramic substrates for decades, it has yet to achieve cost competitiveness with low-cost surface mount technology (SMT). In order to achieve cost competitiveness, new and innovative material systems and process technologies are required.
In many cases, present state-of-the-art flip chip on-board assembly technology is not capable of achieving the high throughputs required for integrated high-volume surface mount technology processing and low-cost electronics packaging. Elimination of processing steps enables high throughput; reduces process complexity, capital equipment requirements, and equipment maintenance; and increases process robustness. Potential processing steps for elimination are flux application, underfill flow, flux residue cleaning and secondary thermal curing of underfill. Highly populated flip chip assemblies and large chips compound current flip chip process limitations.
Based on semiconductor and packaging roadmaps, it is clear that trends for larger devices and higher packaging densities will continue to increase, therefore inhibiting cost-effective flip chip assembly based on conventional process techniques. Underfill flow and cure processes dramatically reduce assembly line throughput, and therefore exert significant pressure on profit margins. This has been verified by cost modeling and analysis comparing a conventional flip chip process, the new low-cost high-throughput process and surface mount assembly.1-5
To enable high-throughput and low-cost processing that is compatible with high-speed SMT assembly, a new process has been developed (Figure 1) in which the overall process flow begins with a known good substrate and die.1,2,3,5 A controlled volume of underfill material is stencil printed over the bond pads on the substrate. Alternatively, the underfill can be high-speed pattern dispensed on the substrate bond pads after solder paste printing. Next, solder paste is printed onto the board using a blind stencil for SMT component assembly. SMT components are placed. The flip chips are then aligned using a vision system to orient the chips relative to global or local bond site fiducials on the substrate. The chips are placed onto the substrate, compressing the liquid underfill making contact with the substrate. A significant advantage here is the elimination of lengthy capillary flow times for conventional underfill processing, particularly with large devices. Finally, the solder interconnects are reflowed simultaneously while curing the polymer underfill encapsulant. Care is taken here to prevent premature gelation of the underfill prior to solder reflow using innovative underfill materials called "no-flow" underfills providing latent gelation such that the cure reaction is inhibited until a critical temperature is reached above the solder liquidus temperature.1-5 It is critical that proper fluxing action be achieved during reflow, which is accomplished by the no-flow underfill.
One of the major advantages of the proposed process is that it increases throughput of flip chip processing. It also transforms a chip-based process into an area-based process, reduces the required number of processing steps, and reduces the ratio of wafer to assembly cost by two to five times conventional flip chip processes.1,2,3
Underfill processing is a time-consuming step in conventional flip chip assembly processes due to the flow mechanism used to fill the standoff gap between the chip and substrate. Conventional techniques utilize a dispensing method where underfill material is dispensed along one edge (or dual adjacent edges) of the chip and allowed to flow under the chip by capillary action. Based on first order principles, the flow time can be estimated using Equation 1,
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assuming the underfill materials are approximately Newtonian, where L is the length of the chip, h is the standoff height, µ is the underfill viscosity, s is the surface tension, and a is the wetting angle of the underfill as shown in Figure 1.
Equation 1 illustrates that the underfill flow time for a given material increases with the square of the chip size and the inverse of the standoff height. As chip sizes increase and standoff heights decrease (due to the decreasing pitch requirements), indicated by the semiconductor packaging roadmaps, underfill flow times will only become compounded, further inhibiting high-throughput production.
With the new low-cost process, the flow time is reduced to the chip placement time, which is given by Equation 2,
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where ho is the initial distance of the chip to the substrate, hf is the final distance of the chip to the substrate once assembled and vplacement is the chip placement velocity (Figure 2).1 Equation 2 illustrates that in the new process, the time required to underfill the chip is no longer dependent on the chip size, chip standoff and underfill properties. In reality, the underfill flow time is eliminated in that the chip placement time would be incurred regardless of whether the underfill is processed or not.
Cost Implications
In order to assess the cost implications of underfill processes and flip chip processing, an activity-based cost model was developed to quantify the costs associated with each step of the flip chip assembly process.1-3 Cost model predictions estimate a two- to five-fold cost reduction over a conventional direct chip attach (DCA) benchmark process using the new low-cost, high-throughput flip chip processes.4 The low-cost next generation flip chip process also reduces the process cycle time by a factor of two to five. In this case, the benchmark DCA process uses conventional capillary flow underfill processing while the low-cost process uses the compression flow underfill process.
Cost savings in the next-generation process stem from a number of factors. The number of process steps is reduced, namely flux application and underfill flow, and secondary underfill cure is eliminated. The next generation process does not require nitrogen inerting during reflow because the encapsulation underfill protects the solder/metallization from oxidation during reflow. Underfill material costs are potentially lower for the next generation process because fillers are not used. Fillers in underfills require precision bimodal distributions of spherical particles. Precision filler particles are major cost drivers in conventional "fast-flow" underfills. Capital equipment and engineering support costs also tend to be lower for the next generation process due to the reduction of process steps and the ability to use underfill application techniques (stencil printing and dispensing), requiring less precision than for conventional processing. This ultimately reduces engineering support required for the underfill process.
Process and Yield Analysis
As with any conventional flip chip process, the potential of void formation in the underfill layer is an area of concern. In the low-cost flip chip process, voids in the underfill can form via three mechanisms. The first is due to outgassing during reflow. Common conditions promoting outgassing voids are dissolved moisture or solvents in the polymer films covering the chip and substrate surfaces (e.g., polyimide passivation, solder mask, FR4, etc.). Heat-treating (e.g., drying) the boards and chips prior to assembly eliminates this type of voiding. Outgassing can also occur within the underfill itself due to excessive ramp rates or temperature exposure during reflow. Higher ramp rates and elevated temperature exposure can cause the underfill constituents to volatilize and cause gas-producing chemical reactions to occur during reflow, resulting in underfill voiding. Such voids can be extensive if the reflow profile is not designed correctly. Figure 3 shows scanning acoustic micrographs of flip chip assemblies produced using the new low-cost, high-throughput process at two different reflow profile ramp rates and peak temperatures. In both cases, the interconnect yield was 100 percent.
The second type of potential void formation occurs during compression flow chip placement and is due to compression voids forming at the chip surface. Simulation results predict that compression voiding is minimal toward the center of the chip, and the number and size of voids increased toward the outer edge of the chip.3 Potential compression voids tend to be less prevalent at higher underfill compression flow pressures. By increasing the degree of cross flow or squeeze flow, potential void formation is reduced. In general, void formation decreases with higher temperatures. Compression voids are also substrate topology dependant. Underfills with lower viscosity and higher surface energies are able to flow into the gaps and cavities more easily, reducing void formation. Exceptions to this trend occur when flow isolation and gravity flow take place, which can be controlled by underfill deposition, shape/geometry and temperature.
The third type of potential void formation is due to capture voids formed during placement of the chip where gas pockets (air in most cases) are captured between the chip and underfill. The primary mechanism for eliminating such voids is entraining the interfacial voids in the cross flow of the underfill to expel the voids toward the chip edge. Controlling the underfill print/dispense geometry is critical to eliminating compression and capture voids. The presence of pressure wells during assembly prevents entertainment of the voids in the cross flow resulting in the presence of capture and compression voids in the final assembly. Preliminary experimental results support the simulation findings and suggest that capture voids are more prevalent in assemblies with a low underfill print height to underfill print area aspect ratio and void formation decreases with increasing aspect ratio.3
Experimentation has shown that with careful control of the underfill geometry, underfill rheology, placement parameters, and reflow process, void formation can be eliminated in the low-cost, high-throughput flip chip assembly process with a relatively wide process window. Experimental analysis has shown no voids in the underfill after chip placement.2 With appropriate control of the underfill geometry, no air pockets form during the placement process. As the chip moves into contact with the underfill, wetting should occur at only one point toward the center of the chip and spread over the surface of the chip as it is depressed farther into the underfill. The surface tension drives the local wetting of the chip, forcing out the air and eliminating capture voids. Having a higher ramped thermal profile has also proven to be effective in void control, for some no-flow materials. Rapid ramp profiles basically remove the standard soak period and follow a near linear ramp up to the reflow peak.
Yield of the low-cost no-flow process has been extremely successful. Test vehicles have consistently produced chip yield percentages of 99.5 percent to 99.9 percent. The capability to assemble flip chips using the low-cost, high-throughput assembly process incorporating no-flow underfill materials has demonstrated a high degree of manufacturability and high throughput. The ability to implement the process on standard SMT equipment, including placement machines and reflow ovens, has been experimentally proven. The placement process prefers lower viscosity, no-flow underfill materials. For a given placement force, as underfill viscosity decreases, the allowable placement velocity increases, improving throughput. The low-cost, high-throughput flip chip assembly process also prefers an underfill with a high surface tension. Yield analysis experiments have demonstrated a wide process window capable of producing high first pass yields.4,5 Excessive underfill volume can result in chip floating.4,5 Chip bump pattern and chip size were found to have relatively little effect on assembly yield. Capture and assembly induced void formation during assembly was also found to be minimal when the appropriate underfill geometry was deposited on the substrate.
Reliability and Failure Mode Analysis
Extensive reliability testing has also been performed on commercial no-flow underfills. Testing included moisture preconditioning, liquid-to-liquid thermal shock, air-to-air thermal cycling, autoclave and temperature humidity aging. Three commercial no-flows and one developmental no-flow underfill were tested.
The reliability performance of the no-flow underfill materials and low-cost, high-throughput flip chip process was modeled using a two-parameter Weibull cumulative distribution function. The distribution function, shown in Equation 3, has two parameters, Q and a.
F(t) = 1 - e-(t ÷ Q)a
Q is the characteristic "life" parameter (approximately a 63 percent cumulative failure), and a is the shape parameter. The shape parameter determines the relative slope of the cumulative failure distribution. An increase in alpha indicates an increase in failure rate.
The Weibull function for the four different materials tested on a group of flip chip test vehicles is detailed in Figure 4, which includes the performance of the material in liquid-to-liquid thermal shock testing. The life parameter and shape parameter in Table 1 shows that material D exhibited the best thermomechanical reliability by surviving 2,130 cycles and having its first failure at 1,000 cycles. In addition, Material D lasted 1,200 cycles before its first failure and exhibited 15 percent cumulative failure at 1,500 cycles.
In a few instances, air bubbles were dispensed onto the board and observed by C-mode scanning acoustical microscopy (C-SAM) analysis. During reliability testing, these air bubbles remained a constant size and did not migrate or initiate delamination cracks. No recognizable changes were observed from C-SAM analysis through 1,100 cycles (Figure 5). In contrast to conventional capillary flow underfills, no-flow underfills exhibit excellent interfacial adhesion. Figure 5 shows typical C-SAM images of underfill A where delamination was not observed prior to 1,800 cycles. Unlike conventional capillary flow underfills, the no-flow underfill materials do not typically fail due to delamination. The most dominant failure mode for the no-flow underfill is solder interconnect fatigue.
Conclusions
Flip chip technology represents a rapidly advancing area in commercial electronics. In order to ensure adequate reliability, flip chip assemblies undergo an underfill encapsulation process in which a polymer material is placed between the chip and substrate. Conventional underfill processing is achieved through chip site to chip site dispensing and relies on underfill capillary action, making it a costly and time-consuming process particularly as device sizes increase and standoff gaps decrease. To address the limitation associated with conventional flip chip processing, a low-cost, high-throughput flip chip process was developed that eliminates the need for time-consuming capillary flow processing by using a compression technique where the underfill is applied prior to chip placement. The innovative process integrates the chip placement and polymer underfill process using a compression or squeeze flow method. It results in significantly lower assembly costs and reduced cycle time. Also, converting the conventional flip chip process to an area-based method allows for an increased throughput at a lower cost. Parametric cost analysis has highlighted the benefits of the low-cost, high-throughput assembly process.
Void formation is a problem that can occur in no-flow underfill processing. Three types of voids have been identified and experimentally observed that have the potential of forming during compression flow chip placement: compression voids, capture voids and outgassing voids. With careful control of underfill properties and process parameters, void formation can be eliminated in the next generation process.
The capability to assemble flip chips using the low-cost, high-throughput assembly process incorporating no-flow underfill materials has been scaled to a high-speed SMT/flip chip assembly line. The process has shown excellent yields and reliable assemblies can be produced using no-flow materials for standard flip chip on laminate applications. Theoretical and experimental data show that there exists a wide processing window for dispensed/printed underfill mass. Accelerated reliability testing results indicate that no-flow materials have the ability to survive in excess of 1,000 air-to-air and liquid-to-liquid cycles (-55 to 125°C). The low-cost high-throughput flip chip process and no flow underfills show great promise for decreasing flip chip cycle time and achieving appropriate reliability for a number of commercial applications.
The authors would like to thank Georgia Tech`s Center for Board Assembly Research and Siemens Energy and Automation for supporting this work. The authors would also like to thank Sonoscan Inc. for use of the model D6000 C-SAM and Flip Chip Technologies for providing the test chips.
References
1. D. F. Baldwin and N. W. Pascarella, "Manufacturing Analysis of Underfill Processing for Low Cost Flip Chip," Journal of Electronics Manufacturing, Vol. 8, No. 1, pp. 39-50, October, 1998.
2. N. W. Pascarella and D. F. Baldwin, "Cost Analysis of Low Cost High Throughput Next Generation Flip Chip Assembly," International Journal of Microcircuits and Electronic Packaging, Vol. 20, pp. 571-577, 1997.
3. N. W. Pascarella and D. F. Baldwin, "Compression Flow Modeling of Underfill Encapsulants for Low Cost Flip Chip Assembly," IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part C, Vol. 21, No. 4, pp. 325-335, October, 1998.
4. L. P. McGovern and D. F. Baldwin, "High-throughput, Low-cost Flip Chip-on-Board Assembly," Electronics Packaging and Production, Vol. 38, No. 2 (1998), pp. 68-76
5. R. Thorpe, L. P. McGovern and D. F. Baldwin, "Analysis of Process Yield in Low Cost Flip Chip on Board Assembly Processes," Thermo-mechanical Characterization of Evolving Packaging Materials and Structure, 1998 ASME International Mechanical Congress and Exposition, Anaheim, CA, November, 1998.
DANIEL F. BALDWIN, Ph.D., and RYAN THORPE can be contacted at the Georgia Institute of Technology, 813 Ferst Drive NW, Atlanta, GA 30332; (404) 894-4135; E-mail: [email protected]. BRIAN J. LEWIS can be contacted at Siemens Energy and Automation Inc., 2875 Northwoods Parkway, Norcross, GA 30071; (404) 894-6351; E-mail: brian. [email protected].
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Figure 1. Graphical detail of a next generation, high-throughput flip chip process combined with standard SMT components.
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Figure 2. Flow diagrams of conventional capillary flow (l) and compression flow (r) underfills.
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Figure 3. Scanning acoustic micrographs of low-cost next generation flip chip assemblies demonstrating outgassing voids due to excessive reflow ramp rates. (Left) High ramp rate. (Right) Low ramp rate profile.
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Figure 4. Weibull comparison plot of underfills A, B, C and D subjected to LLTS.
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Figure 5. Delamination and void growth over 1,800 thermal cycles.