Ceramic Technology Meets Market Demands
01/01/2000
Substrates ready for next generation of high-density CSPs.
YOSHINOBU KUNITOMO
The global demand for smaller electronic products is pushing manufacturers to use higher-density components. For companies that must develop them, an added complexity lies in meeting marketplace demands for higher quality and improved reliability, which, in turn, involves overcoming considerable technological challenges beginning with the creation of comprehensive research and development programs.
At Matsushita Electronic Corp., a program to create a new generation of high-density, high-reliability components has led to the development of a ceramic-substrate-based, small-lead-pitch semiconductor package called the Ceramic Chip Scale Package (C•CSP). Although similar to a Land Grid Array (LGA) package, the C•CSP does not use solder spheres as the electrical contacts. Rather, its design emphasis benefits from continuing research and analysis of cost issues together with an exploration of differences in coeYcient of thermal expansion (CTE) between the ceramic substrate and common printed circuit board (PCB) materials (Figure 1).
Overall Design Objectives
In the initial development of the C•CSP package, the following specific attributes were identified as necessary: "extreme" thinness, no lead on pins or solder pads, easy mountability (flip-chip mounting capability), low cost and small package size. Other requirements included high electrical performance, flexible pin location and good handleability. Such requirements mandated ceramic as the material of choice. What follows is a discussion of that conclusion together with why a solderless interconnect design is also key in meeting the overall objectives.
The Benefits of Eliminating Solder Contacts
The call for extreme package thinness necessarily dictated the elimination of solder spheres. Reason: They typically add to overall thickness an amount equal to 40 percent to 60 percent of the contact pitch itself. With their elimination, however, the chip "floats" on molten solder paste during the reflow process in which surface tension provides a degree of self-alignment of chip to board. Thus, for a chip with a lead pitch of 1.00 mm, misalignments as high as 0.40 mm will automatically adjust to the correct position. Result: Existing mounters can be used for placing C•CSPs.
By contrast, conventional LGAs are more diYcult to mount with high accuracy, i.e., they self-align less effectively than the C•CSP package. With a conventional LGA, one of the functions of the solder sphere is to "compensate" for any non-planarity in the package itself or in the PCB surface. Another is to make up for differences in CTE between the mounted chip and its substrate. With the bumpless C•CSP, a high degree of package planarity must be achieved with a thickness that does not exceed that of the printed solder paste. This dimension must also take into account any warpage of the board caused by reflow temperatures.
Only ceramic has achieved the degree of flatness required. In the development, multilayer processes have gained a flatness of better than 10 mm after the co-firing process, while the CTE between the mounted chip and its ceramic carrier was measured as low as 4 ppm/°C (Table 1).
Analysis of Reliability after CTE Effects
The combination of a ceramic chip carrier and the absence of solder bumps might seem to create reliability problems when the PCB`s CTE differs from that of the carrier during the reflow process. Generally, solder bumps help relieve some of the stress due to differences in rates of expansion. However, if their use were absolutely necessary, then conventional quad flat packs (QFPs) with copper lead frames would often crack for that reason. Yet it is well-known that this is not the case. Reason: The strain caused by CTE differences is not absorbed entirely by the solder.
Figure 2 shows C•CSP reliability test results as a function of ceramic substrate thickness and land diameter.
The Stud-bump-bonding Process
The viability of using flip-chip mounting with the stud-bump-bonding (SBB) process was explored as a part of Matsushita`s overall CSP research program. The advantage of the SBB method is its use of a conventional aluminum integrated circuit (IC) chip pad designed for wire bonding. This approach permits the packaging of integrators to take chips from different semiconductor manufacturers and package them easily on the same substrate using flip-chip techniques. Table 2 shows the necessary specs for a ceramic chip carrier to ensure compatibility with the SBB mounting method. The carrier material is alumina - a mature, field-proven material with which a number of improvements have been made to facilitate the manufacture of CSPs. Such improvements include enhancement of the lamination process, an improvement of gravity distribution of the green tape and a reduction of dimensional variations due to shrinkage after co-firing.
Other Advantages of Ceramic
An important package characteristic for manufacturers is the maximum allowable time interval between removal of the product from its protective packaging and completion of the reflow process. When this period is short, storage becomes a problem, i.e., it will be necessary to prebake the chips, adding a manufacturing step. Ceramic CSPs, on the other hand, enjoy a considerable advantage here, clearing infrared reflow (three times) at 235°C after 168 hours at 85°C and 65 percent relative humidity.
Another important package characteristic is directed at how well ceramic handles the heat necessary to rework or repair a PCB on which it is mounted. In high-density-designed products, such as cellular telephones, the duration of heat application must be tightly controlled to avoid melting the solder on adjacent packages. In addition, the challenge of short heat duration is compounded in array packages, such as LGAs and CSPs, where hot air cannot be applied directly to the solder (the package itself obtrudes). Accordingly, to facilitate reworking, the array package must have a low thermal resistance between the package`s top (where the heat is applied) and its bottom (where the solder will flow). Ceramic material not only meets this requirement but has a heat-conduction path between chip and solder of only 0.05 mm, yielding a resin and ceramic substrate combination thickness of 0.4 mm.
Two other areas in which ceramic exhibits improved characteristics are sheet resistivity and lead inductance. Table 3 compares a number of characteristics of a QFP with a CSP having an alumina ceramic substrate. Note how the CSP - partly via its shorter connection and wire lengths - exhibits lower resistance and lower conductance through 200 MHz. Similarly, ceramic technology also minimizes peeling even when internal routing and vias are close to the outer edge of the carrier. In this manner, ceramic makes it possible to increase the number of lands that can service a given chip design. Lastly, another advantage is that ceramic substrate technology permits one via to be stacked directly on another (Table 4).
Conclusion
Early in the development of CSPs, users were concerned about visual inspection of solder joints after the package is mounted on the board. Unlike with QFPs, where solder connections are clearly visible, those of CSPs are directly under the package itself, making a visual inspection virtually impossible. However, upon further consideration, it became clear that other array packages, such as fine-pitch BGAs, deliver high yield rates that generally neutralize concern over inspections.
In the early semiconductor industry, much of the packaging was based on ceramics. However, as cost and handling considerations were taken into account, packaging moved to plastic, leading to the perception that ceramic was no longer a viable packaging choice. Now it can be seen that current multilayer ceramic packaging technology is essential for the high-density and -reliability levels demanded by today`s marketplaces.
YOSHINOBU KUNITOMO, package development manager, can be contacted at System LSI Division, Semiconductor Company, Matsushita Electronic Corporation, 1, Kotari-yakemachi, Nagaokakyo, Kyoto, 617-8520, Japan; (075) 956-9562; Fax: (075) 953-7514; E-mail: [email protected].
 |
Figure 1. Package configurations of the quad flat pack, ball grid array and chip-scale package. The C.CSP design will seek to reconcile differences of thermal expansion between materials.
 |
 |
 |
Figure 2. CTE of carrier controls the second level reliability.
 |