ECTC wrap-up
08/01/2001
Reliability of key concern at ECTC
BY KATHLEEN M. PETERSON
In late May, engineers, researchers, analysts and, yes, even editors, descended upon Walt Disney World in Orlando, Fla., for the 51st Electronic Components and Technology Conference (ECTC). In the midst of a semiconductor downturn, attendees were optimistic regarding technologies that are currently in development - nearly every sentence that began, "It's been a tough year..." ended with "...but we're looking forward to a rebound in 2002."
In brighter times, it seemed that the overarching emphasis in product development was the desire to make packages and devices smaller, faster and less expensive. While these concerns are still paramount, the conference sessions at the ECTC underscored an increased emphasis on reliability and functionality.
Double-bump WL-CSP
In this vein, Beth Keser of Motorola SPS (Tempe, Ariz.) presented a paper entitled "Encapsulated Double-bump WL-CSP: Design and Reliability." A new type of wafer-level package (WLP), in which an encapsulation material is applied directly to a bumped wafer, was introduced. This method eliminates the underfill process and is said to protect all the bumps on a wafer at once in a batch process. The key to "double bumping" is bumping the wafer a second time with balls after the application of an encapsulant to create a double-bump structure to increase overall height and improve reliability.
 Schematic of the double-bump WLP process flow. |
Redistributing bond pads from the die periphery to an area array through the use of BCB and redistribution metal (either sputtered aluminum or electroplated copper with a TiW adhesion layer) can eliminate the need for an interposer. Keser reported that micro Moirè interferometry has shown that the encapsulation layer aids in distributing stress throughout the wafer-level bumps.
To determine the reliability advantages of the encapsulated double-bump structure (in comparison to a single-bump WL-CSP), both single-bump and double-bump WL-CSPs were subjected to accelerated life testing and analyzed. The packages underwent liquid-to-liquid thermal shock, air-to-air thermal shock, air-to-air thermal cycles, high-temperature storage and autoclave. To date, double-bump parts have survived 240 hours of autoclave, while their single-bump counterparts experienced first failure after 192 hours. Shock and cycling tests are continuing, and double-bump packages are exhibiting high reliability. Additionally, tests are being conducted to analyze board-level reliability through air-to-air thermal cycling and temperature-humidity-bias.
This approach to WLP is said to simplify processing and reduce cost. The addition of filler to the encapsulation material is essential to decrease the CTE of the encapsulation layer to match the solder joints and increase the stiffness. The use of preformed balls for both levels of bumps reportedly increases the overall collapse height, thus improving board-level reliability.
Optical-I/O Chip Packaging
At this year's ECTC, as in the industry at large, optoelectronic components and packaging were hot topics. The conference dedicated a short course to optoelectronics, as well as paper sessions on optical networks, high-speed packaging and optical interconnects. Even without an official headcount, the opto events were among the most highly attended at this year's conference - some sessions were standing room only.
 Optical-I/O chip packaging concept. |
One such presentation was "SMT-compatible Optical-I/O Chip Packaging for Chip-level Optical Interconnects" by Yuzo Ishii of NTT Telecommunications Energy Laboratories (Kanagawa, Japan). Ishii proposed a solution for implementing an economical chip-to-chip optical interconnection by doing the following: 1) integrating silicon ASICs with GaAs optoelectronic devices by bump bonding, 2) surface mounting optoelectronic packages on a PCB, 3) implementing optical paths for connecting chips as an interlayer of the PCB, and 4) coupling the chip and the board through a narrow air gap with a wide and collimated optical beam. This method reportedly can replace high-speed electronic wiring and requires no optical fibers or connectors on the board.
With the use of optical-I/O chip packaging, PCB-based optoelectronic board technology is expected to speed package development and allow for earlier introduction. In the future, such boards may contain not only polymeric waveguides, but also various passive optical components, such as arrayed waveguide gratings, splitters, couplers, attenuators and connectors.
The wide and collimated beam that is proposed addresses the need for tolerance against misalignment that often occurs in the SMT process. A 1.25 Gb/s VCSEL-to-PD coupling experiment and tolerances of ± 50 µm were successfully demonstrated.
Bumpless Interconnect
In response to the growing need for ultra high-density and fine-pitch interconnections, researchers at The University of Tokyo, Research Center for Science and Technology, have proposed bumpless interconnection for next-generation system packaging. Tadaotomo Suga presented a paper entitled "Bump-less Interconnect for Next Generation System Packaging" and defined "bumpless interconnect" as an interconnect of a size below 10 µm pitch between chip and substrate, or between chip and chip.
 Schematic of a packaging concept using bumpless interconnect. |
With bumpless bonding, two structures composed of interconnections and insulating layers are bonded directly without a bump-like electrode. Such ultra fine-pitch interconnection may allow for the interconnection of two different devices, such as analog, RF, digital or even MEMS devices in a vertical direction. Bumpless interconnect will require extremely thin chip and substrate, so that thermal stress can be reduced through the bending of the bonded pair.
Another novel approach that must be taken with bumpless interconnect involves the bonding technology. Conventional bonding methods, such as soldering or thermal compression, cannot achieve bumpless interconnect. A surface-activated bonding (SAB) method must be employed; the concept of SAB is based on the fact that two atomically clean solid surfaces under contact develop an extremely strong adhesive force. Researchers at the university have used argon fast atom beams to obtain the clean surfaces at room temperature. Reportedly, surface activation can meet the demands for high reliability and high-density interconnection.
ECTC 2002, San Diego
The 52nd Electronic Components and Technology Conference, co-sponsored by the Electronic Components Association (a sector of the Electronic Industries Association) and the Components, Packaging and Manufacturing Technology Society of the IEEE, will be held May 28-31, 2002, at the Sheraton Harbor Island in San Diego, California.
Proposed 500-word abstracts describing the scope, content and key points of the proposed paper will be accepted until October 15, 2001. Abstracts should be submitted to Steve J. Bezuk, Kyocera America Inc., 8611 Balboa Ave., San Diego, CA 92123; Fax: 208-439-4316; E-mail: [email protected]; Web site: www.ectc.net. Topics may include advanced packaging, components and RF, connectors and contacts, education, interconnections, manufacturing technology, materials and processing, modeling and simulation, optoelectronics, and quality and reliability. Poster presentations are also encouraged. Individuals interested in teaching short courses should contact Larry Mann at 864-409-5746 or [email protected].