Lithography requirements for 300-mm WLP
07/01/2001
Photodefinable polyimide addresses packaging challenges
BY MANISH RANJAN, STEVEN KAY AND WARREN FLACK
Even though flip chip technology has been in existence for 30 years, the ramp in volume bumping has only begun during the past few years. C4 (controlled collapse chip connection) technology was developed by IBM in the mid 1960s, but this technology was primarily limited to higher temperature solder. Recent underfill material developments have ensured successful transition to eutectic tin-lead solder bump technology.1 Widespread adoption of flip chip technology has been driven by increased integrated circuit (IC) performance and form factor advantages.
The current growth in the advanced packaging market also coincides with the transition to 300-mm wafer fabrication. The economics of scale justify the use of advanced packaging processes for 300-mm wafers. To ensure optimal cost of ownership (COO) for 300-mm wafer processing, it is imperative to pay careful attention to individual process steps and the associated equipment selection criterion. This article discusses some of the challenges encountered during the photolithography step for wafer fabrication, as well as the feasibility and performance of an aqueous developable photosensitive polyimide. The exposure was conducted using a 1X stepper. The polyimide film thickness uniformity and critical dimension (CD) control were analyzed to determine the process capability for 300-mm wafers. It was observed that this polyimide could be coated to better than two-percent uniformity across the 300-mm wafer.2
Photolithography Materials
The ramp in 300-mm wafer fabrication is having a significant impact on the development of photolithographic materials, equipment and associated processes. Devices fabricated on 300-mm wafers are being packaged using advanced packaging techniques, such as flip chip and wafer-level chip-scale packages (WLCSP). Figure 1 shows the various process steps used in wafer bumping.
 Figure 1. Wafer bumping process sequence. |
Polyimides are being used for passivation stress relief and soft error protection for advanced packages.3 Polyimides also provide excellent adhesion to the chip passivation and the under bump metallization (UBM). Photosensitive and non-photosensitive polyimides are the two major categories of the polyimides in use.
Conventional, or non-photosensitive, polyimides were historically used as passivation stress buffers (PSB). Polyimides, both photosensitive and non-photosensitive, are usually applied to the wafer using a spin-dispense technique. The major difference comes from the complexity of the process following the coating. A non-photosensitve polyimide requires that a layer of photoresist be applied to the polyimide layer and exposed using a lithography tool. The photoresist is developed to remove the exposed areas, enabling etching of the polyimide. The non-photosensitive polyimide has a significant level of process complexity and poor sidewall profile quality resulting from the isotropic polyimide etch process.
 Figure 2. Process comparison of conventional and photodefinable polyimide. |
Photosensitive polyimide products were introduced to address these issues. These materials may be directly exposed by the photolithography tool, which results in reduction of manufacturing processes and decreases cycle time for the production facility. Figure 2 shows the process step comparison for the conventional polyimide and the positive acting photosensitive polyimide process. Photosensitive polyimides also provide superior resolution and improved sidewall profiles in comparison to conventional polyimides.
The photolithography requirements for thick photosensitive polyimides can be addressed using optical lithography equipment. 1X steppers offer advantages for processing thick photosensitive polyimides, primarily because of good depth of focus, imaging and alignment characteristics. There can also be advantages in throughput, automation and flexibility with 1X steppers.
Wafer Bumping at 300 mm
Flip chip and WLCSP have witnessed increased adoption in the electronics packaging industry because of electrical, thermal and form factor advantages. The adoption of bumping and WLCSP is clearly evident in the emerging 300-mm device fabrication market. Figure 3 shows the demand for 300-mm wafer bumping compared to the total 300-mm wafer fabrication forecast. It is estimated that the production cost savings for the 300-mm microprocessor production lines could be as high as 30 percent over 200-mm lines.4 These economies of scale apply to wafer bumping as well.
 Figure 3. 300-mm wafer bumping trends. (Source: Tech Search International) |
The drive toward 300-mm wafer bumping is also enhanced by the types of devices being produced on 300-mm wafers - microprocessors, DRAMs and large ASICs, all of which are leading the drive toward bump and WLCSP as the predominate packaging method. According to the market research firm TechSearch International, 60 to 70 percent of the devices fabricated on 300-mm wafers will require some form of bumping.
The transition to 300-mm wafer fabrication poses unique challenges for the manufacturing equipment. This is especially the case when considering the lithography process step.
Lithography Challenges
One of the most important factors in the selection of a lithography tool is the ability to print defect-free images on a wafer, thereby eliminating the lithography tool as a yield detractor. Key performance issues associated with the lithography step at 300-mm wafer bump processing include yield optimization, meeting the imaging requirements of the redistribution level and maintaining optimal cost performance while insuring that technical requirements are met.
Potential yield losses encountered during resist imaging using traditional bump lithography equipment (contact or proximity printers) include resist damage from incidental wafer to photomask contact, alignment errors introduced by expansion of the photomask during the single prolonged exposure and defects caused by residual resist on the photomask.5 The need to eliminate these yield losses and improve the process yields has resulted in the widespread acceptance of stepper technology. Steppers eliminate the need for close wafer to photomask contact. The ability to auto align along with the precision stage control technology ensures superior alignment. Steppers also eliminate alignment errors induced during the single prolonged exposure required by contact or proximity printers.
The growing use of a redistribution layer to use greater chip area is creating tighter pitch and smaller resolution requirements for the flip chip and WLCSP process. 1X stepper technology provides good technical solutions with system resolution better than 2.0 µm and alignment accuracy below 0.5 µm.
In addition to the considerations previously mentioned, semiconductor manufacturers using proximity/contact aligners need to address photomask costs and availability concerns to support wafer fabrication at 300 mm. Incorporating stepper technology addresses this issue because steppers use fixed size reticles for imaging of all substrate sizes.
In the packaging market, outsourcing manufacturing as a method to reduce costs is quite common. With the outsourcing model, flexibility becomes a key component of any equipment's capabilities. Many packaging foundries are supporting various wafer sizes, including 300 mm, making wafer size flexibility a desirable equipment feature. These foundries require tools that can handle multiple wafer sizes and accommodate the different wafer thicknesses. The ability to process warped wafers is also important to minimize potential yield loss. All of these requirements are driving the industry toward more flexible lithography platforms to keep equipment costs at a minimum.
Characterization of Aqueous Developable Photosensitive Polyimide
Photosensitive polyimides provide good processability with planarization, low dielectric constants for high-speed performance and high temperature resistance characteristics.3 Photosensitive polyimides are used for passivation stress relief, soft error protection for memory devices and as a final passivation layer for the interconnect bumping operations. The use of photosensitive polymers lowers the manufacturing costs by eliminating several process steps and increasing the available manufacturing capacity. The following experiment was designed to investigate the performance of this polyimide material for a 300-mm application using 1X stepper technology.
Reticle design and manufacture: The 1X reticle used during the exposure consisted of two fields of 10.0 mm by 10.0 mm, one of each polarity to support both the positive and negative acting polyimides. Each field contained horizontal and vertical grouped patterns of lines and spaces from 2 to 12 µm in 2 µm size increments, and 15, 20, 30, 40, 50 and 60 µm structures. Patterns of equal lines and spaces, as well as isolated lines, were included for all structure sizes. Each isolated line was separated from its nearest neighbor by a minimum of five times the line width.2 All of the line structures were 5 mm in length to facilitate cross-sectional SEM analysis. There was no data biasing applied to the design data, and CDs were held to within ± 0.03 µm of a nominal 2.0 µm chrome line.
 Figure 5. a) Process window for 3 µm space in 9.8 µm thick aqueous developable photosensitive polyimide. b) The process envelope represents ±10 percent CD control limits. |
Lithography equipment: A 1X stepper was used during the photolithography exposure process sequence. This tool employs broadband optics and can illuminate a wide spectral range (100 nm), including both the g-line and i-line wavelengths. It is also capable of switching between narrower illumination wavelengths (only gh or i line) if required. A low numerical aperture (0.16) improves the depth of focus, providing a wide process window to process the thick films required for bump applications. The tool incorporates a dynamic focus system that enables improved side wall angles and enhanced aspect ratios.
Processing conditions: SEMI standard 300-mm ultra flat silicon wafers were used for characterizing the aqueous developable photosensitive polyimide (HDMicrosystems HD-8001 polyimide). It was observed that there is approximately 50-percent shrinkage between the pre-bake and final cure thickness of this polyimide. As the normal PSB thickness is between 5 and 10 µm, this material was evaluated at 9.6 µm pre-bake thickness. The polyimide thickness and uniformity were measured on a thin-film thickness measurement tool.2
Results and discussion: CD measurements of isolated spaces were taken at 18,000x magnification. Multiple space widths were measured top-down on the SEM equipment over the entire focus and exposure matrix. The CD data was analyzed using Prodata software.
Wafer coating and development: 300-mm wafers were coated with the polyimide at a spin speed of 1,000 rpm to obtain the desired thickness of 9.6 µm after coat. The polyimide uniformity was measured at 49 points across the 300-mm wafer. It was observed that the polyimide coating uniformity was better than 2 percent across the wafer.
The coating uniformity for the same wafer was measured after the immersion develop process. It was noted that the film uniformity degraded to 6.4 percent. Most of the non-uniformity was attributed to the slots in the wafer cassette that was used for the immersion develop process. The developer flow to the wafer surface was restricted by this cassette design. It should be noted that the film uniformity could be drastically improved by using the puddle develop process on a 300-mm production track.
Polyimide characterization: The stepper exposed the wafers from 400 to 650 mJ/cm2 in increments of 25 mJ/cm2. The focus was varied from -8 to +2 µm in increments of 1 µm. This polyimide demonstrated a 2 µm resolution for isolated spaces, as shown in Figure 4. The sidewall angle is approximately 68 degrees and is independent of spaces down to 2 µm. This polyimide also exhibits good process characteristics. Figure 5a illustrates the process window plots for 3 µm space features. The gray shaded region demonstrates a 10-percent control limit for this space. This figure also shows the largest process window that fits within the envelope. It is observed that the exposure energy at the center of the process window is 465 mJ/cm2 and the focus is -0.6 µm. Figure 5b shows a curve that summarizes all of the rectangles. It is observed that the maximum exposure latitude is 7.3 percent, while the maximum focus latitude is 8.7 µm.2
The CD uniformity was measured at 238 points across the 300-mm wafer. The average CD for this sample wafer was 8.59 µm with a 3 sigma of 1.25 µm. The across-wafer uniformity was 14 percent. The CD uniformity could be significantly improved using a puddle develop process on a 300-mm production track.
Conclusion
Traditional lithography techniques, such as contact and proximity printing, face significant challenges for advanced packaging lithography applications. Stepper technology provides superior technical performance and potential cost of ownership savings. 1X stepper performance was examined, as was the feasibility of processing photosensitive polyimides on 300-mm wafers. It was noted that the film uniformity after develop and the CD uniformity are highly dependant on the develop process. It was shown that a 1X stepper offers significant process latitude and short exposure times for this polyimide. This also demonstrates the performance and flexibility of the 1X lithography platform for 300 mm. AP
References
- P. Elenius, "Flip Chip Bumping for IC Packaging Contractors," Flip Chip Technologies white paper, www.flipchip.com.
- W. Flack et al., "Characterization Study of an Aqueous Developable Photosensitive Polyimide on 300 mm Wafers," Optical Microlithography XIV Proceedings SPIE, p. 4346, 2001.
- K. Horie et al., Photosensitive Polyimides: Fundamentals and Applications, Technomic Publishing Company, July 1995, pp. 15-16.
- J. Irwin, "300 mm Wafer Processing Tools," Solid State Technology, October 2000, pp. 79-80.
- S. Kay et al., "300 mm Wafer Stepper for Bump and Wafer Level Chip Scale Packaging Applications," Pan Pacific Microelectronics Symposium 2001 Proceedings, 2001.
Manish Ranjan is senior product marketing manager, Steven Kay is director of product marketing, packaging technology, and Warren Flack is director of applications and reticle engineering at Ultratech Stepper Inc. For more information, contact Steven Kay, 3050 Zanker Road, San Jose, CA 95134; 408-321-8835; Fax: 408-325-6444; E-mail: [email protected].