Advanced tools for HDI design
03/01/2001
Build-up substrates and next-generation design tools Contribute to the miniaturization of electronics.
BY KENT McLEROTH
As the electronic products industry continues to push the envelope of extreme miniaturization, product development teams are being forced further into the realm of high density interconnect. Design techniques and substrates labeled exotic only a few years ago are now considered mainstream. In particular, build-up substrate usage has grown dramatically, and is now found in a large percentage of high-production electronic products.
Build-up substrates saw their first large-scale usage in Japan's competitive consumer electronics market to meet the need for small, lightweight, high-performance products. Product markets for mobile telephones, notebook computers and digital camcorders have become so competitive that relatively small differences in size, performance, price and time-to-market routinely make the difference between a successful product line and one that fails. For this reason, new technologies, such as build-up substrates and next-generation design tools, are needed within these competitive markets.
 Figure 1. Representation of a substrate, illustrating core layers, build-up layers and allowable via types. |
The proliferation of build-up has caused design teams to rethink both their design approach and the software tools used to accomplish these designs. This article is intended to help electronic design teams move from traditional substrates and design techniques into incorporating the latest technological advances in high density interconnect.
What is Build-up?
Build-up substrates are now available from a wide variety of vendors, encompassing many configurations. There are, however, several attributes that are common among build-up types, including:
- Size reduction (lower substrate size, weight and volume)
- Increased wiring density, including closer component spacing and smaller component footprint
- Higher densities, which translate to lower cost per connection
- Improved electrical performance, including a tenfold reduction in parasitics from through-hole designs
- Lower RFI/EMI (ground planes can be closer to, or on the surface, and distributed capacitance is enhanced)
- Greater design efficiency (microvias allow for easier part placement on both sides of the board, and "via in pad" allows for easier escape routing and higher densities).
EDA Tool Requirements
 Figure 2. Example of a staggered via. Note the size of the core via in relation to the conformal (micro) vias and the distances maintained between. |
Successfully designing for build-up requires an electronic design automation (EDA) tool that supports the unique rules and requirements necessary for these substrates. The most fundamental of these requirements is the ability of the tool to accept and support build-up layer structures. In many cases, materials vary among layers requiring layer-specific and layer-to-layer specific rules. In addition, multiple via structures must be supported within a single design technology. Typically, these may include conformal (micro) vias, inner conformal vias, skipped (landless) vias, through-core vias and through vias (Figure 1).
An EDA tool should have parameters in place to support these via types, and use them in the correct design situation. Each substrate configuration requires specific rules for each via type. Most manufacturing methods limit the via combinations that can be used and minimum distances between them, requiring techniques, such as staggered, spiraled and stepped vias (Figure 2).
 Figure 3. Build-up specific rules, including center-to-center via pitch, must be supported by the EDA tool. |
Build-up design requires that additional rules, not required by traditional substrates, be supported. Without such build-up specific rules, an engineer runs the risk of designing a product that cannot be manufactured. Selecting an EDA tool intended for design on build-up substrates is a requirement for designing accurately and efficiently.
One example of a build-up specific rule is center-to-center via pitch (Figure 3). Center-to-center via pitch is required to ensure that the via configuration is correct through the entire substrate. Once the basic layer and via conventions are defined, the tool must support, by layer, all of the necessary clearances required by the substrate materials. This includes clearances for each via type individually (Figure 4). An EDA tool should support these individual clearances to take full advantage of the characteristics of the substrate.
 Figure 4. Clearance rules defined individually for each via type. |
Additional rules that must be supported include trace spacing by layer, landless via and through-hole clearances, component pad and resist clearances, substrate edge by layer, and standard PCB rule requirements.
Build-up technologies can provide dramatic space savings in the routing area, so routing functions should be able to maximize the opportunity. Microvias free up space that would otherwise be used by the larger through-hole vias, so EDA tools should exploit these advantages wherever possible. Intelligent "search via" capabilities allow staggered via patterns to avoid obstacles up through the substrate, assisting in providing the highest possible routing density. In many cases, "meshed" planes are required to enhance both fabrication yield and EMI performance (Figure 5). An EDA tool should have the ability to mesh solid planes in a variety of patterns.
It is also helpful if an EDA tool provides a user interface that allows the engineer to work in a three-dimensional environment. As substrate stackups become increasingly complex, it is more difficult to work effectively in a traditional two-dimensional environment.
 Figure 5. Meshed plane. |
Figure 6, a traditional top-down view through the substrate, is acceptable when designing for a standard substrate. When designing for build-up, however, it becomes difficult to discern how the various vias are structured through the layers. Figure 7 illustrates a clearer view of the picture by providing the three-dimensional design environment.
Technology Partnerships
There are now several fabricators offering build-up substrates, each with their own unique set of advantages and design rule requirements. These requirements are changing as rapidly as the electronic products they support. It is therefore no longer practical for a design engineer to stay abreast of every substrate technology and the corresponding design rule requirements. This gap in technology awareness has spawned new relationships between EDA software providers and substrate manufacturers to deliver vendor-approved design technology kits to the market.
Such kits contain vendor-specific design rules, etch requirements, layer stackups, material information and via structures in a format understandable by the design tool. They are now available from a number of leading substrate vendors for the design engineering community.
There are advantages of using a vendor-approved design rule kit. Primarily, an engineer is assured of designing a product that can be manufactured. Rather than taking the time to thoroughly research all of the rules and requirements of a given substrate, an engineer may simply plug the appropriate technology kit into the EDA tool and begin the design. The kits, which are approved by both the EDA vendor and the substrate manufacturer, ensure the design will meet the manufacturing rules.
 Figure 7. 3-D view of via patterns reveals a clear picture of the routing strategy. |
For instance, designs begin by selecting the appropriate substrate. Each substrate type has its own advantages with regard to size, weight,
density, circuit performance and cost. Once selected, an engineer can browse the library of substrate technologies. The appropriate technology kit may then be selected and plugged into a graphical technology viewer/editor for review. These editors are significantly more effective than the traditional text-based "rule matrix," as they provide a clear picture of the technology requirements.
Once the technology and rule information has been reviewed in the technology editor, the information may be extracted into a format understandable by the EDA tool. Traditionally, rule files, layer creation, layer mapping, pad and padstack creation have been separate, manual efforts within the EDA tool. The graphical technology editor can perform all of these tasks in one step, ensuring that the technology and rules considerations specified by the substrate manufacturer are met by the design.
Summary
It cannot be reasonably expected that a design tool intended for traditional substrates can be used effectively to design for build-up technology. Designing for build-up using a traditional printed circuit board design tool can be akin to using a screwdriver to drive a nail. To complete the task efficiently, the proper tool should be selected. Items to look for in a build-up design tool include:
- Support for build-up specific features, including layer stackups, micro vias, build-up via combinations, and mesh planes
- Support for build-up specific rules, including layer-to-layer clearances and center-to-center via type distances
- Graphical technology editor
- Partnerships between the EDA vendor and substrate manufacturers.
The advent of next-generation EDA tools and technology partnerships removes much of the uncertainty of high density interconnect design, allowing design teams to take full advantage of leading-edge technology.
KENT McLEROTH, technical marketing manager, can be contacted at Zuken Inc., 238 Littleton Road, Suite 100, Westford, MA 01886; 978-692-4900; Fax: 978-692-4725; E-mail: [email protected].
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