C4 makes way for electroplated bumps
03/01/2001
FLIP CHIP INTERCONNECT
COVER ARTICLE
Until recently, controlled collapse chip connection bump technology, developed in the late 1960s, provided a reliable interconnect for high-performance, leading-edge microprocessors. As device and wafer fabrication methods have progressed, however, evaporative bump technology has been increasingly unable to meet product demands. Electroplated bump technology, while not new, has emerged as one of the most desirable options currently available to meet increased interconnect requirements.
For depositing bumps, electroplating offers the ability to reduce bump pitch, the flexibility to deposit different bump alloys, the capability to produce economical low-alpha bumps, and the potential to accommodate the demands of 300mm wafer processing. The technology's first three attributes can be instrumental in reducing overall system cost and enabling the migration of products from wire bond to flip chip, while keeping up with constant device shrinks. For 300mm wafer processing, electroplate offers a photo-based technology that can more readily accommodate the increase in wafer size.
As is usually the case with relatively immature technology, however, manufacturing electroplated bumps has its challenges. This article compares electroplate's attributes to those of evaporative bump technology, and describes challenges that could limit electroplate's widespread use.
Evaporated bump process
The controlled collapse chip connection (C4) evaporative bump process, patented by IBM in the early 1960s, provided a method for producing multichip modules for the mainframe computer market and single chip packages for high-performance computing [1].
The evaporative process deposits solder bumps by selectively depositing metals through a molybdenum (Mo) shadow mask. The initial process step is an argon (Ar) sputter etch to remove the die bond pad oxidation and ensure low electrical contact resistance. The evaporation of chrome (Cr)/chrome-copper (Cr-Cu)/copper (Cu)/gold (Au) forms the under bump metallization (UBM). This structure acts as a hermetic seal, provides an electrically conductive diffusion barrier, and establishes a good mechanical base for the solder bump.
 Figure 1. Evaporative bump process. |
Following the UBM layer deposition, the next step is to evaporate lead (Pb), followed by tin (Sn), to form the bulk of the bump. In the unreflowed state, the bump heights are consistent across the wafer, providing a good interface for probing or burn-in. In the final step, the bump is reflowed, which homogenizes the PbSn solder and allows the Sn to form an intermetallic compound with the Cu of the UBM, providing the necessary adhesion between the die and the bump (Fig. 1).
Electroplated bump process
Some of the earliest bumps using electroplate as a deposition method appeared in the late 1960s and early 1970s with tape automated bonding (TAB) [2]. Gold was the most common material used for TAB bumps and the technology was primarily accepted by the Japanese for its high-productivity potential in the manufacture of low-cost consumer products like calculators and watches. Since that time, electroplate has seen numerous derivations of the original TAB gold bump process in the evolution of technology leading to bumped wafers for flip chip components [3, 4].
 Figure 2. Electroplate bump process. |
An effective approach to the electroplate process for bumping wafers begins with a thorough cleaning of the wafer surface materials to ensure good electrical contact and adhesion of the bump to the wafer. After cleaning, the first metal layer of the bump's UBM base structure is sputtered on the wafer in blanket form. This first metal layer often uses titanium in combination with other refractory metals to provide optimum electrical contact to the device; this produces strong adhesion to the wafer surface constituents (polyimide, glass passivation, bond pad metallization, etc.), and acts as a diffusion barrier between the solder bump and the die metallization. Next, a thin metal seed layer, such as copper, is deposited in blanket form to provide a low-resistance electrical path for the electroplating process.
To define the remaining bump structures that are to be selectively electroplated on top of the sputtered UBM, a thick photoresist coating, align, expose, and develop process is performed. After the photo process, it is necessary to electroplate more copper to provide a mechanically stable base for the bump; the solder bump alloy of choice is then plated to complete the structure. After plating is complete, the photoresist is stripped and the UBM layers are wet etched away. Ashing, fluxing, reflowing, and cleaning complete the process (Fig. 2).
Evaporated vs. electroplated bumps
Bump pitch. Evaporated bump technology has extendibility issues when bump pitch is decreased below 225µm. The method used to fix the molybdenum mask to the wafer results in nonuniform clamping at the wafer edge and bowing of the mask across the wafer. Further, if the mask is not in physical contact with the wafer, metals can be deposited underneath, causing leakage or shorting between bumps. As bump pitch and diameters decrease, the mask must become thinner to accommodate the finer features. The thinner mask is thus not as rigid, which aggravates the nonuniform contact phenomenon. Another factor affecting fine pitch capability is the significant tolerance stack-up in the manual mask-to-wafer alignment procedure. This tolerance stack-up can prevent the UBM from covering the via, causing a nonhermetic seal and potential electromigration issues.
 Figure 3. 100µm-pitch bumps. |
One of the most significant advantages of the electroplate bumping process is that it relies on photolithographic means to define the UBM and solder bump. Photolithography, in combination with a high-performance photoresist, permits extremely small structure definition and does not limit practical minimum bump pitch. For electroplate, bump pitch is limited more by assembly and reliability considerations than by the formation of the bump. Bumps have been successfully produced at 100µm pitch (Fig. 3). Figure 4 shows that, as device size decreases, bump pitch must also decrease to prevent possible die size increases for a given interconnect count.
Solder alloys and bump over memory. Evaporated bump technology is fundamentally limited to high-lead, low-tin solders, such as 95/5 Pb/Sn or 97/3 Pb/Sn, in the conventional Pb/Sn solder system. Tin possesses a relatively low vapor pressure, limiting the effective rate at which it can be evaporated. The unacceptable trade-offs are either long solder deposition times, or solder melting on the wafer because of excessive tin source power levels.
Electroplate, on the other hand, is not limited to high-lead, low-tin solders, and can quite readily process solders of any lead-tin composition as long as a chemistry is available. Electroplating is also adaptable to plating "no-lead" binary or tertiary alloys, which is becoming a requirement in many electronics assembly processes.
The electroplate process also provides a benefit for products requiring bump over memory. Bump over memory provides a way to minimize die size in situations where significant memory is on board the die. Bump over memory requires that low-alpha radiation materials be used in the bump to prevent soft errors and potential data corruption of memory cells. Lead is the primary offender with high-alpha emission levels relative to tin. Electroplate is a selective deposition process, so very little lead is wasted compared to evaporative technology. Therefore, electroplating of low-alpha-emitting lead is economically feasible.
300mm wafer-bumping capability. One significant challenge to wafer-level packaging development will be the introduction of the 300mm wafer. It is expected that high-performance microprocessors/memory will be the first to use 300mm wafers, which suggests that flip chip will be required when this technology is introduced. Today, evaporation technology does not appear to be extendible to 300mm wafers because of its dependence on molybdenum shadow masks. These masks have temperature compensation incorporated into their design to offset the mismatch in mask and wafer coefficients of thermal expansion (CTEs) that, at larger wafer diameters, aggravates the tendency for misalignment. As mentioned earlier, mask-to-wafer alignment is a manual process and is therefore somewhat rudimentary.
 Figure 4. Die size reductions and effect on bump pitch. |
Electroplate accommodates 300mm wafers quite well because photolithography eliminates CTE mismatch considerations. There is much work to be done, however, before the first electroplate-bumped 300mm wafer is produced. Attributes of bump height uniformity and composition across a wafer must be examined closely. Flow dynamics, cup design, and electrode design will be critical factors in controlling 300mm wafer electroplate.
Electroplating challenges
Although electroplate bumping offers many advantages over evaporation methods, it presents several challenges for initial implementation. The following are some of its more obvious problems.
Wafer contamination. Incoming wafers have exposed metal bond pads with a thin oxide layer on the surface, and an initial plasma pre-clean is performed to remove the oxidation layer. Additional contaminants that need to be removed to initiate successful bumping are often found on the wafer surface, however. Contamination on the passivation surface may not allow proper adhesion of the UBM to the passivation or may cause underfill delamination at the die surface during assembly. Additionally, any residue left in the vias because of an error in the wafer fabrication process or from improper removal of residual organic photoresist may cause improper plating or contaminate a plating bath.
UBM structure to work with all alloys. Electronic components are reflowed multiple times during the process of bumping, assembly, and final attach to the motherboard. During these multiple reflows, tin in the solder migrates to the UBM interface and forms intermetallics that provide a robust adhesion structure. Although tin plays this important role in forming intermetallics, if the thermal budget is exceeded, the tin can consume the UBM and lead to reliability failures. The specific UBM, bump alloy, and downstream thermal processing must be completely understood to maintain a reliable interconnect.
Uniformity. Size and coplanarity of the completed bumps are dependent on a number of factors, including mask via sizing, plating uniformity, flow characteristics, resist uniformity, and plating current density. The variance in plating and bump height uniformity may be plating's largest challenge. Solution flow patterns, cup design, contact clip methodology, and current densities within a plating system must be optimized to achieve ideal uniformity across a wafer and, more importantly, across the die. Current densities are highest near the cathodes and, in general, plating is proportional to the current density as long as the plating is not diffusion limited. This tends to cause higher current densities and therefore faster plating rates at the edge of the wafer as compared to the center.
Sputtered film etch. In the electroplate process, the UBM and seed metal materials are selectively etched from the wafer in the presence of solder. The primary concerns with this process are the undercut of the UBM structure and the oxidation of the solder because of the wet etch chemistries. Etch chemistries can preferentially attack the UBM structure and reduce the diameter of the UBM, diminishing the bump's mechanical integrity. Undercut can be affected by flow characteristics in the bath, location in a wafer boat, and etch chemistries. Tight process controls must be established to ensure that the proper etch attributes are achieved. Another important attribute of the etch process is the effect on the oxidation of the plated solder. The ability to successfully reflow bumps into their proper shape is compromised in cases where extreme oxidation occurs. This may cause non-wet problems during the process of joining the die to the component substrate.
Reliability. Bumps play a crucial role in component reliability. Evaporated C4 bumps have a long history of reliability on ceramic substrates; many companies have used C4 technology for producing millions of devices. On the other hand, electroplated bumps do not have the extensive field data to support their widespread acceptance. Companies deciding to implement electroplate bump technology will be required to provide sufficient data demonstrating reliability. UBM design, structure, and materials, and the bond pad under the bump are as important as the robustness of the solder bump itself. The UBM/bump structure cannot be disassociated from the polyimide, underfill, and substrate with which it interfaces. It is the careful and knowledgeable combination of these complex constituents that provides the key to acceptable reliability. As device and reliability requirements vary by market and application, some companies will find it easier to implement electroplated technology than will others.
Conclusion
Finding one wafer-level bumping process to accommodate all device and package roadmaps is a major objective. The flexibility of the electroplate bumping process has the potential to meet projected future needs. All major high-performance IC manufacturers either use or plan to use electroplating to service their advanced products. This process possesses the flexibility of depositing different solder and lead-free alloys, of producing bumps with very tight pitches, of using different metal films and sequences, and of obtaining heights and diameters customized to accommodate any product requirement.
Electroplate bumping also appears to be the best potential process for wafer-level bumping of next-generation 300mm wafers. Most bumping processes are capital intensive; a prudent philosophy is to employ a single high-volume, high-yielding bump process to achieve a cost-effective product. This high-volume process must be flexible enough to accommodate any product requirements without adding or omitting major capital equipment sets.
While the electroplate bumping process appears to be a good solution, there is still room for process improvements and equipment and process optimization. The process yield must be greater than 99% because the starting material is a completed IC. It is important to understand not only the cost of bumping, but the total system cost also. By making trade-offs when using concurrent engineering, a lower system cost may be achieved.
References
- E.M. Davis, W.E. Harding, R.S. Schwartz, J.J. Corning,"Solid Logic Technology: Versatile High Performance Microelectronics," IBM Journal of Research and Development, p. 102, 1964.
- A.D. Aird, "Method of Manufacturing a Semiconductor Device Utilizing a Flexible Carrier," US Patent 3,689,991, 1972.
- T. Kamei, M. Nakamura, "Hybrid IC Structures Using Solder Reflow Technology," 28th Electronic Components Conference Proceedings, pp. 172-182, 1978.
- C.J. Speerschneider, J.M. Lee, "Solder Bump Reflow Tape Automated Bonding," Proceedings 2nd ASM International Electronic Materials and Processing Congress, pp. 7-12, 1989.
For more information, contact John Franka, Motorola SPS, 3501 Ed Blue stein Blvd., Austin, TX 78721; ph 512/933-2148, fax 512/933-6981, e-mail [email protected].
David Clegg, Rebecca Cole, John Franka, Doug Mitchell, Dave Wontor, Motorola Semiconductor Products Sector, Austin, Texas