XinTec Expands Shellcase CSP Technology
12/01/2002
LSI Logic Develops Innovative Wire Bonding
MILPITAS, CALIF.
LSI Logic developed a packaging technology that allows for wire bonding on top of active circuitry. This capability results in die size reductions up to 50 percent since the chip does not have to be designed with a ring of bond pads around the exterior of the active area. The new design approach also includes three rows of staggered wire bond pads, allowing an effective wire bonding pitch of 27 µm.
The new technology, called "Pad on I/O," is an industry first for chips with copper interconnects and low-k dielectric materials, and LSI Logic has developed it for its 0.11 µm process technology. The approach includes metal and dielectric structures in the chip that build in mechanical robustness.
Along with these silicon process upgrades, new assembly processes also were developed. Stan Mihelcic, manager of advanced packaging solutions at LSI Logic, told Advanced Packaging that standard assembly equipment was used, so any packaging subcontractor can assemble chips with the Pad on I/O technology.
Mihelcic also said that LSI Logic previously implemented low-k dielectric with aluminum interconnect in its 0.18 µm process technology, so the company had extensive experience working with the more fragile dielectric materials.
In general, the silicon process technology has outpaced the packaging technology, so the industry has not been able to take full advantage of on-chip process shrinks. By placing fine-pitch wire bonding pads on top of active circuitry created with the latest process technology, the die size reductions can keep pace with the feature size reductions.
Packaging Update from Intel
BY JULIA GOLDSTEIN
SAN JOSE, CALIF. — The Intel Developers' Forum held here included an update on Intel's packaging strategy from Koushik Banerjee, manager of substrate technology research for assembly technology development.
In "Advanced Cooling Strategies," Banerjee reviewed thermal management challenges as die power and component density increase.
Banerjee's overview of packaging technology discussed the need for silicon and packaging integration, such as choosing substrates with coefficient of thermal expansion (CTE) closely matched to Si, developing novel underfill processes and improving equipment to handle tighter bump pitches. New package architectures such as the bumpless build-up layer (BBUL) introduced by Intel last year are one solution to enable high-speed processors.
Package interconnect scaling is reaching limits as line width and spacing move below 20 µm and the number of laser drilled vias per layer increases beyond 2,000. Intel is working on a "breakthrough interconnect solution" to overcome these limits.
Several chip scale packages (CSP) were presented for building systems-in-a-package (SiP). Two-die stacks currently are in production, and four-die stacks with a package height of 1.0 mm are being sampled. Another option uses a wire-bonded memory die stacked on top of a flipped logic chip to enable higher frequencies in a smaller package. Many logic and memory chip configurations were shown in a new folded, stacked CSP currently in development. The folded CSP effectively allows two stacked die packages connected with solder balls to be stacked together to form a single SiP.
Fairchild and Philips Form Packaging Alliance
SOUTH PORTLAND, MAINE, AND EINDHOVEN, THE NETHERLANDS — Fairchild Semiconductor and Royal Philips Electronics, competitors in the logic integrated circuit (IC) market, announced that they will be standardizing their package formats with each other.
The agreement between Fairchild and Philips calls for them to become a "multi-source supplier" for the tiny packages that standard logic devices use. Fairchild's leading edge package is MicroPak, a leadless package that is 65 percent smaller than the familiar SC70 package. The Philips DQFN (Depopulated very thin Quad Flat-pack No-lead) is a match for higher lead count devices in the logic arena, and it is 75 percent smaller than existing TSSOP packages.
A key advantage of the alliance is that it creates an automatic second source for Fairchild and Philips products. Instead of comparable chips in different package formats, which is a logistical problem for users, the functionally similar chips from Fairchild and Philips will be drop-in replacements for each other. The intent is to provide a competitive advantage for both suppliers since a second source is required in many logic applications.
XinTec Expands Shellcase CSP Technology
SCHÄRDING, AUSTRIA — EV Group (EVG), a manufacturer of various wafer processing equipment, completed another equipment purchase agreement with XinTec Inc. of Taiwan. This order contains a full production line including an 8" production mask aligner and an automated resist coating system for advanced wafer-level CSPs (WLCSP). XinTec Inc. is an exclusive joint venture (JV) partner of Shellcase in the Asia/Pacific Region.
Sheldon Chen, vice president of XinTec, noted the technical capabilities and flexibility of the EVG equipment, saying, "EVG's systems provide us with the capabilities needed to supply the latest design in chip packages to the industry. The tools are highly customizable and permit us to process various substrates and materials without reconfiguration. This gives us tremendous flexibility and advantages for our technology."
 EVG's 150 Coating Machine is an automated resist coating system for advanced WLCSPs. |
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The JV parnter Shellcase, located in Israel, is a prominent supplier of WLCSP technology. The patented Shellcase CSP approach uses a glass-silicon-glass sandwich whose capabilities include image sensing through the actual packaging structure.
CPS High-thermal Conductivity Materials
CHARTLEY, MASS. — Ceramics Process Systems Corp. (CPS) announced the production availability of high-thermal conductivity composite components for various commercial, industrial and military electronics applications.
An aluminum-silicon-carbide (AlSiC) matrix is the base material for these components because its CTE can be engineered to match various packaging materials, such as an organic or ceramic substrate. It also offers a weight reduction of about two-thirds compared to copper and features an isotropic thermal conductivity value of 180 W/mK.
The new material is created by inserting extremely high-thermal conductivity materials, such as highly oriented pyrolytic graphite (HOPG), into an AlSiC metal matrix composite. The resulting components can act as internal heat spreaders within the AlSiC substrate, package lid or package body. Applications include lid components for high-power server processors, substrates used for radio frequency (RF) and microwave packaging, substrates for power semiconductors, and military special-purpose ICs built on SiC, SiN and other high-performance devices.
HOPG offers an in-plane thermal conductivity value of 1,350 W/mK, and it can be manufactured in sizes measuring from 0.25 x 0.25" to 6.0 x 10.0" and larger. These high-thermal conductivity HOPG wafers are inserted into a pre-form in the casting process, in a predetermined location within the AlSiC component being manufactured. The finished component will then offer an overall in-plane thermal conductivity value in excess of 1,000 W/mK.
ASE Announces 300 mm Flip Chip Production
SANTA CLARA, CALIF. — Advanced Semiconductor Engineering Inc. (ASE) announced that its 300 mm wafer flip chip bumping line is ready for volume production. ASE's development effort for 300 mm solder bumping was completed in November 2001, and customers have been running qualification tests at the ASE facility this year.
Investment in 300 mm capability has continued in spite of the recent downturn, and according to ASE, the migration to 300 mm wafers has been an increasing focus for cost reduction because of the difficulties of reducing per-die costs with shrinking feature size.
J.J. Lee, vice president of research and development (R&D) at ASE Group, said "With industry migration to 300 mm, ASE is already moving ahead by establishing processes and equipment to handle these larger wafers." ASE offers 300 mm wafer packaging and testing services including substrate design and fabrication, bumping, wafer sorting, flip chip packaging, and final test.
Amkor Expands MLF Capacity
CHANDLER, ARIZ. — Amkor Technology is expanding its capacity for MicroLeadFrame (MLF) packaging to accommodate the demand in low pin count wireless applications. Amkor's capacity is projected to be 75 million units per month by the end of 2002.
 Amkor's MLF package. |
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Sean Crowley, Amkor's vice president of advanced lead frame products, cited some specific applications: "MLF has quickly become a critical package solution for cell phones, wireless LAN and Bluetooth." He also noted the thermal and electrical performance as key features.
MLF is Amkor's version of a semiconductor package with the generic nomenclature of QFN, which stands for "quad, flat, no-lead." These are "leadless" lead frame packages, meaning that the lead is flush on the bottom of the molded package, which is soldered directly onto the board. Crowley sees these packages replacing the leaded SO packages, saying, "We believe a reasonable percentage of SO packages could move to MLF format, which should significantly expand the market for MLF."
IC Plating: Status and History
BY CHRISTINE F. DELLA MONACA
Since the 1970s, IC plating has evolved from manual operations to fully automated, process-controlled wafer and back-end plating lines.
In the "old days," process control involved manually dunking racks and barrels full of IC components into larger vats, while management hoped the parts and operators would still work on the other side, said Bance Hom of MEPTEC. Another major dilemma was the prevalence of plating fires, which, at a company Hom worked at, resulted in an assembly plant burning down.
In the 1980s, the industry evolved from bright tin-plated components to matte tin-plated ones, resulting in a more reliable, solderable and environmentally sound plating solution, Hom added. The revision to Mil-Spec 38510, intended to redirect the industry from plating to solder dipping, specified a 2 to 50 percent lead requirement, which had environmental concerns. When packaging moved toward a pitch of 0.050" or less, solder dipping went by the wayside.
With high-speed automation and process control developments, especially in Asia, plating came back, but the 5 percent lead requirement meant tin/lead solder plate had to be implemented. Lead in solution can mean hazardous lead sludge. "I personally don't believe we should be moving our high-volume manufacturing overseas for cost advantages and then turning these countries into toxic lead dumps," Hom stated.
The current lead-free movement may provide some salvation, Hom said, but the currently hot markets of military and defense are waffling about eliminating the lead requirements and accepting lead-free solutions like matte tin. At the same time, she added, the most recent survey in Asia showed 75 to 80 percent of companies favor matte tin as their environmental solution.
Movers and shakers
People
 Joachim Gudat |
Dage Precision Industries (Fremont, Calif. and Aylesbury, UK) appointed Joachim Gudat as sales manager Europe for the X-ray products of Dage Semiconductor GmbH in Germany.
Casey Krawiec joined StratEdge (San Diego) as senior account manager.
MEMGen Corp. (Burbank, Calif.), a leader in micro device and micro system fabrication, appointed Elliott R. Brown to its advisory board.
Newport Corp. (Irvine, Calif.) appointed Nonoy Sornillo to sales manager for Newport's MRSI Advanced Packaging products in the Philippines.
 Paul Lukaniec |
V.J. Electronix, a div. of V.J. Technologies Inc., (Bohemia, N.Y.) appointed Paul Lukaniec as manager of North American sales for their complete line of digital X-ray inspection systems.
Companies
Veeco Instruments Inc. (Woodbury, N.Y.) and FEI Co. (Hillsboro, Ore.) signed a definitive merger agreement to combine the companies into a world leader in 3-D metrology and process equipment. FEI will become a wholly owned subsidiary of Veeco, and Veeco will be renamed Veeco FEI Inc.
Anvik Corp. (Hawthorne, N.Y.) installed a wide-field lithography system, the HexScan 1100 SWE, at an undisclosed Fortune 100 company.
Amkor Technology Inc. (Chandler, Ariz.) consummated its share purchase transaction with Dongbu Group under which Dongbu purchased 20 million shares of common stock of Anam Semiconductor Inc. from Amkor.