New Tessera Stacked Packages
11/01/2002
SAN JOSE, CALIF. — Tessera Technologies developed a package stacking technology that addresses business and logistical issues created by multichip integration.
The Tessera approach allows packaged and tested chips to be stacked within the footprint of a single chip package. The ability to test the chips in a packaged format before stacking them eliminates the drawbacks of either bare die testing or compound yield loss from untested chips.
The package stacking technology, called the µZ Fold-over package by Tessera, is enabled by the substrate in the package at the bottom of the stack. It is designed to extend beyond the package body and be folded onto the top of the package. Designed into the folded-over part of the substrate is a standard memory interface for attaching a packaged memory device on top with a standard surface mount process.
Stacking packages instead of chips allows ICs from different suppliers to be integrated without concern for procuring the chips in wafer format. It also allows standard burn-in processes — and different ones for each device — to be used before they are stacked.
Bruce McWilliams, Tessera's CEO, illustrated another potential benefit of this packaging approach. He told Advanced Packaging that Tessera redesigned a wireless phone with the new packages, and this allowed the main PCB to be four layers instead of six, saving a dollar in the production of each phone. With the price pressure on mobile electronics, that is a significant advantage.
LTCC, Other Substrates Prominent at IMAPS
Denver, Colorado
The booth traffic was generally sluggish, but there was plenty of interesting technology and business to see at the 35th annual IMAPS microelectronics symposium here. More than one person guessed that the usual good technical sessions distracted some people from the exhibits.
A few key trends that arose included the continuing focus on substrate technology. Low-temperature co-fired ceramic (LTCC) was probably the highest-profile topic throughout the sessions and on the floor. The Ceramic Interconnect Initiative (CII) even announced its top 10 developments in ceramic technology, and LTCC developments dominated the list. In the top spot was the "HeraLock" material from Heraeus. This LTCC material has virtually zero shrinkage in the X-Y plane during processing.
The CII list of top 10 developments is:
- Heraeus HeraLock — self-constrained LTCC material
- Cerel — electrophoretic deposition of ceramic materials
- CAD Design Software — design tools
- Midcom and Electro Science Laboratories — ferrite transformer
- Kyocera — ceramic package with low-resistance interconnect
- NEC — 60 GHz LTCC module
- Satcon — thin film LTCC termination
- Philips, NSC, Motorola — Bluetooth and other LTCC products
- Plextek — 21.3 GHz LTCC oscillator.
Along with the ceramic technologies on display, several suppliers also discussed organic substrates that are pushing the envelope.
GIL Technologies, for example, announced the commercial availability of a new high-performance substrate material in thicknesses of 60 and 80 µm. John Gardner, VP of global sales and marketing at GIL, told Advanced Packaging that the material is a patented blended polymer resin, and the engineering that goes into it results in properties superior to other substrate options. The water absorption is very low, for example, and the thermal stability is better than other materials. For electrical performance, the dissipation factor is lower than BT and FR-4, making it a good choice for GaAs and other high-speed requirements.
Parelec also had some interesting substrate technology to discuss at IMAPS. Parelec makes conductive inks for high-density interconnect applications, and its critical technology is the ability to create traces with electrical conductivity approaching plated metals, but doing it with high-speed and low-cost printing processes. A challenge with this approach can be ink adhesion to the substrate, but Parelec has developed a polyimide that solves this, according to Parelec's VP of Technology Brian Conaghan.
Also in the polyimide realm, Akiho Hirahata of CMK in Japan told Advanced Packaging about the capabilities of CMK's materials. Its substrates target tape ball grid arrays (TBGA) and chip on film for LCDs, with one or two metal layers on polyimide. CMK's roadmap shows 10 µm lines and spaces four years from now.
As always, the technology available to see at the IMAPS symposium made it a worthwhile event.
Honeywell Establishes Process Integration Center in Singapore
SINGAPORE — Honeywell established the Honeywell Electronic Materials (HEM) Star Center in Singapore, a facility dedicated to materials and process integration of its thermal management and electrical interconnect products. The 5,000 sq. ft. facility is located in the Changi Business Park, and the work there is focused on products and processes used in the assembly of advanced ball grid array (BGA) and flip chip packages.
Jack Bolick, VP and GM of HEM, emphasized the importance of the location, saying, "It is essential to be close to our customers. More than 80 percent of advanced BGA and flip chip packaging occurs in East and Southeast Asia, so the Star Center in Singapore is the optimum strategic location for us to collaborate fully with our customers in meeting their technology needs."
MTBS Introduces High-speed Flip Chip Packages
SAN JOSE, CALIF. — MTBSolutions Inc. (MTBS) introduced flip chip packages for ultra-high-speed and RF applications with capabilities up to 40 GHz. ASE Electronics Malaysia, a subsidiary of ASE Test Ltd., will provide assembly services on these large bandwidth packages in body sizes from 7 x 7 mm to 52.5 x 52.5 mm.
"The most challenging aspect of these developments has been in the electrical design of the structures used within the package itself," said Bob Hilton, CTO.
A key part of the package technology is the high-density, high-speed technology provided by AMITEC. The substrate material has a dielectric constant of 2.55, and the substrate allows solid filled vias from the silicon to the signal or ground planes. The solid via provides lower resistance and inductance than plated through-hole vias, and the AMITEC process also results in less dimensional variation and more consistent signal performance.
Dow Corning Expands Product Scope
MIDLAND, MICH. — Dow Corning Electronics, currently a significant supplier of thermal management materials, is expanding its product line to include what it terms "fabricated" thermal materials. This includes phase-change materials in formats — pads and films — that end users can incorporate directly into their products.
Dow Corning's decision to work in a larger portion of the supply chain is an understandable move for a materials supplier with a healthy market share. Tim Adams, market development manager at Dow Corning, told Advanced Packaging that the materials typically are only about 10 to 15 percent of the cost of the thermal management product, limiting how much the business can grow. Manufacturing the final product increases the opportunity substantially, both because of the market size and the typical profit margin.
Flip Chip on Leadframe Progress
CITY OF INDUSTRY, CALIF. — Carsem decreased the minimum bond pad pitch possible in large production volumes by about 50 percent with its flip chip on leadframe (FCOL) packages. The technology has been extended to the point where bumped chips with 200 mm pitch bond pads can be incorporated into the packages.
FCOL consists of flipping a bumped die onto a leadframe-based package and then molding it using standard plastic package assembly processes. According to Carsem, the technology allows in the same package size a die that is up to four times larger in area than a wire-bonded version.
The new fine-pitch capability opens up new applications for the package. According to Paul Smith, Carsem's director of marketing, "We expect to see our volumes reach hundreds of millions per year over the next few years, especially in our MLP [micro leadframe package] family."
Enhanced WLP Technology
WILLOW GROVE, PA. — The Flip Chip Div. of Kulicke & Soffa (K&S) introduced a wafer-level package (WLP) technology that extends the capability and improves the performance of its WLP products.
The key to the technology, named "Spheron" by K&S, is a 5 mm thick, low-k dielectric film that is deposited before the under bump metallization (UBM) and solder structure above are created. The film was developed for low modulus, high elongation value, good adhesion to organic and inorganic materials, and good tolerance to manufacturing tolerances.
According to K&S, reliability is enhanced by more than 30 percent compared to
conventional WLPs because the polymer film is planarized, which addresses step coverage and topology issues in the UBM and solder structures.