Wafer-level Packaging Evolves and Grows

10/01/2002

BY JEFFREY C. DEMMIN

SUNNYVALE, CALIF. MEPTEC's latest one-day symposium, "International Wafer- level Packaging Conference: The Convergence of Fab and Assembly," focused on one of the hottest topics in the industry. Wafer-level packaging (WLP) technology continues to progress as applications are beginning to expand, and speakers approached the field from all angles at the popular event.

WLP Drivers and Status

Conference Chair Thomas Di Stefano of Decision Track gave the introductory talk, "Wafer-level Packaging Takes Shape," and one key insight explains how chip and package designers might start working together. He pointed out that the power and ground distribution on all but the smallest chips becomes a concern with the shrinking interconnect geometries on chips.

According to Di Stefano, the RC delay issues are an increasing problem because the resistance scales inversely with the square of the lithographic dimension (the on-chip wire is both narrower and thinner) but the capacitance is roughly constant because the line's width and the distance to the next layer are changing by the same ratio. Consequently, RC delay is accelerating faster than overall chip technology.

The solution, said Di Stefano, is to take the power/ground distribution up in the packaging levels in a wafer-level package. This allows more flexibility and better performance because of the geometries that are possible in the interconnect in the packaging layers. This means that the chip and the package must be designed together.

One area where most speakers agreed was the nature of current and upcoming WLP applications. Scott Barrett of Kulicke & Soffa Flip Chip Div. (FCD) pointed out how just a few years ago the target for WLP was high-end applications, but it recently has become clear that WLP as it exists today is most appropriate for low-pincount, small chips. The volume applications identified by Linda Matthew of TechSearch confirmed this trend.

Barrett also cited that the data shows 90 percent of FCD's current products do not use any redistribution — they are "bump on I/O" structures. One WLP technology that has proliferated most successfully, National Semiconductor's MicroSMD, does not include redistribution, but it has found many applications anyway. Luu Nguyen of National Semiconductors gave the latest update there, including detailed information on surface mount processes for these WLPs.

Wafer-level Burn-in Challenges

Wafer-level burn-in and test was another important topic at MEPTEC's conference, and Di Stefano indicated that there might be more leverage in the cost equation there than in the WLP processes. The simplification possible in the burn-in and test area is significant, but there are some key roadblocks. Steve Greathouse of Intel said that wafer-level burn-in will not work for microprocessors for the foreseeable future because of the thermal challenge. The total power when running all the chips on a wafer currently is prohibitive on Intel's cooling technology roadmap. Carl Buck at Aehr Test Systems told Advanced Packaging that there are ways to work around that, but the benefit of wafer-level processing is compromised.

Bob Million of Million & Associates gave an excellent review of the many wafer-level burn-in technologies being developed, and he also cited thermal issues as a significant concern. The many efforts reviewed include Motorola/Gore/TEL, Matsushita, FormFactor, Gryphics and Aehr Test/NHK/Electroglas.

Phil Marcoux of Tru-Si coined a new term to describe what might develop in WLP. He envisioned a "middle-end" of semiconductor manufacturing, with WLP processes being handled by a separate set of companies between the traditional front-end of the wafer fab and the back-end of packaging. Unitive was an example he cited of such a company. Perhaps the variety of processing will cause the industry to disperse into more categories before it converges into one.