Wafer Bumping Solutions Consumer to advanced applications
10/01/2002
BY TOSHIO HAMANO AND ALEX PAPALEXIS
Wafer bumping technology recently has attracted considerable attention in the high-end computing and networking markets, primarily because this technology has enabled high performance for high-density MPU, ASIC and memory device structures. Flip chip ball grid array (FCBGA) is a package type that uses solder bumping interconnection while simultaneously allowing for an area-array configuration (Figure 1). This ensures signal and power/ground integrity far superior to conventional peripheral wire bonding interconnection.1
For commodity or consumer products, such as cellular phones, the package size is of vital importance. Chip scale packages (CSP) already are well accepted in the industry. However, the search is still on for even smaller solutions, such as wafer-level CSPs (WL-CSP), which are a true chip size package. Another example, bumped die for flip chip on board (FCOB) assembly, also can reduce a product's final size.
Wafer Bumping Processes
There are three primary wafer bumping processes — evaporation, electroplating and screen printing. Evaporation methods require substantial investment in capital equipment and typically entail high cost of ownership. Electroplating methods are known to drive the trend for finer bump pitch, but some solder materials are not suitable because of electroplating bath constraints. Screen printing methods typically are the most cost efficient; but there can be severe limitations on bump height when the bump pitch is less than 200 μm.
A recently developed advanced printing (AP) bump method uses a photosensitive resist film and provides a solution that can address the entire range of applications, from consumer to very high end. This partly is due to the advantage of an advanced screen printing bumping process, which enables both a bump height comparable to electroplating methods and a cost structure that is competitive with standard screen printing.
 Figure 1. Solder bump array and two FCBGA package configurations (glass ceramic [left] substrate and a build-up [right] substrate). |
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Key material, design and process considerations in solder bumping include:
- Bump Material: high-temperature, eutectic and lead-free
- Bump Pitch: substrate compatibility (bismaleimide triazine [BT], build-up, high-thermal expansion glass ceramic, etc.)
- Bump Height: first-level reliability
- Bump Configuration: area-array (MPU/ASIC) or peripheral (memory/analog)
- Bump Process: wafer-level (evaporation, electroplating, and screen printing) or single chip (dimple plate)
- Cost.
The demand for lead-free bumping materials has increased because of the Waste Electric and Electronic Equipment (WEEE) & Restriction of Hazardous Substances (ROHS) Directive proposals in Europe.2 Furthermore, lead-free bumps minimize alpha-particle effects on memory macros in system-on-chip (SoC) devices. It has been demonstrated that as many as 11,000 bumps can be fabricated on a single die at 153 μm bump pitch using lead-free bumps on a copper wiring CMOS CPU.
Another innovative method of applying solder bumps involves a unique single chip solder bumping technology.3 This method is ideal for wafer "shuttle" services, i.e., fabrication of different devices on a single wafer for one or many users who share the initial tooling costs. Because a "shuttle" wafer must be singulated prior to individual user or customer shipment, single chip solder bumping is an effective method to apply bumps separately on each device.
 Figure 2. Advanced bumping capabilities, showing a) 100 μm pitch bumps and b) bumps on a 100 μm thick wafer. |
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Additional achievements include the development of bump pitch as low as 100 μm and bumping on wafers as thin as 100 μm (Figure 2). These advances allow for FCOB to become a very viable solution for system miniaturization. Naturally, an optimal solution also would have to consider the total cost for bumping, substrates, packaging, assembly, testing and board-level assembly.
One way to address bumping costs, the new AP bumping method, uses photosensitive resist film.4
 Figure 3. Process flow for a) AP bumping compared to b) traditional screen printing. |
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AP Bumping Method
AP expands current capabilities for more uniform fine-pitch bumps. The height of a bump fabricated using AP bumping is similar to that enabled using electroplating and at a cost competitive to typical screen printing methods. For example, AP can produce bumps with a height of 105 μm at a 200 μm pitch, while electroplating produces bumps 100 μm in height, and screen printing yields bumps only 75 μm tall.
 Figure 4. Bump shear test after high-temperature storage at 150°C for electroless and electroplated Ni UBM. |
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The process flow for AP bumping is shown in Figure 3. One important aspect of this technology is its use of a unique photosensitive resist film selected for its outstanding properties in patterning, as well as the fact that it can withstand the high temperatures required for bump formation while still responding well to stripping by alkaline solvents. Furthermore, due to the use of dry film openings at patterning, the height uniformity of the bumps is improved vastly.
All under bump metallurgy (UBM) is deposited by sputtering titanium/copper (Ti/Cu) and electroplating nickel (Ni). Additionally, electroless Ni plating can be used to form the UBM 5, which allows for additional cost reductions when combined with AP bumping because it avoids sputtering and the associated costly equipment.
 Figure 5. Pull test results after high-temperature storage for a) electroless and b) electroplated Ni UBM. |
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The materials used to achieve lead-free bumps prevent intermetallic diffusion. For example, data collected when performing a shear/pull test on the bumps show excellent strength for both electroplated and electroless Ni UBM. In particular, the shear test results exhibit no deterioration due to intermetallic diffusion even after storage at 150°C for 1,200 hours (Figure 4). In fact, the failure occurred within the solder. Figure 5 shows no pull strength deterioration after a pressure cooker test at 121°C and 100 percent relative humidity for 504 hours. As expected, the data shows higher values for Ni UBM when electroplated as compared to electroless, mainly due to pad size differences.
Figure 6 depicts reliability data for AP bumping on both types of UBM deposition. In one case, a test die with electroplated Ni UBM was assembled in a FCBGA package using a glass ceramic substrate of high coefficient of thermal expansion. Another die, with electroless Ni, was attached to a test board made of a BT resin. The moisture sensitivity level was Level 4 as per JEDEC standards. Excellent results were confirmed at all tests, including temperature cycling (T/C), pressure cooker with storage/bias (PTHS and PTHS w/bias), and high-temperature storage/bias (HTS and TB-AC w/bias).
 Figure 6. Reliability results of AP bump using a) electro Ni UBM and (b) electroless Ni UBM. |
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Future Trends and Roadmap
The International Technology Roadmap for Semiconductors (ITRS), 2001 Edition predicts bump pitches at 150 μm in 2003, 130 μm in 2005 and 120 μm in 2007.6 The target is to achieve a finer bump pitch of 90 μm by 2010. Yet, we already have fabricated eutectic bumps for fast SRAM devices in FCBGA packages at a bump pitch of 119 and 153 μm using BT resin substrates while maintaining 250 μm bump pitch. Solder bumping was selected to reduce inductance at the interconnect level and thus improves signal integrity in certain applications.
Additionally, stud bumping technology recently has been applied to stacked multichip package assembly to combine memory with logic devices with logic in the same package using flip chip bonding.7 In fact, wafer bumping at 100 μm pitch can be used for various memory devices to control bump coplanarity during flip chip bonding. This technique is particularly advantageous when used in conjunction with thin wafers, especially in portable but feature-rich applications, such as cellular phones, where both space and cost savings are critical.
REFERENCES
- T. Hamano, "Flip Chip Technology and Market Trend," MEPTEC Report, November/December 2000, pp. 25-28.
- 2 T. Hamano, "Keep the Reliability, Dump the Lead: Japanese Companies Accelerate Lead-free Packaging," Chip Scale Review, November/December 2001, pp. 68-69.
- 3 I. Yamaguchi, et al., "Solder Bump Transcription Using a Dimple-Plate Method," Pan Pacific Microelectronics Symposium, pp. 351-354, 1997.
- 4 S. Sakuyama, et al., "Solder Bumping Technology for Wafer-scale Packaging" (in Japanese), 7th Symposium on Microjoining and Assembly Technology in Electronics (Mate 2001), pp. 285-290, 2001.
- 5 Y. Makino, et al., "Study of Process and Reliability for Electroless Nickel Plating UBM on Aluminum" (in Japanese), Microelectronics Symposium 1998 (MES'98), pp. 113-116.
- 6 "International Technology Roadmap for Semiconductors," 2001 Edition.
- 7 A. Takashima, "Technologies for SiP" (in Japanese), JISSO/PROTEC Forum Japan 2001, pp. 80-85.
Toshio Hamano, director of Advanced Packaging Technology R&D Dept., may be contacted at Fujitsu Ltd., (81) 0594-24-5528; Fax: (81) 0594-24-1577; E-mail: [email protected]. Alex Papalexis, manager of Advanced Packaging Technology Group, may be contacted at Fujitsu Microelectronics America at (408) 922-9000; E-mail: [email protected].
Illustration by Gregor Bernard