Design for reliability
10/01/2002
BY TONG YAN TEE
Computer-aided engineering (CAE) has become critical in the reliability analysis of semiconductor packages due to the recent advances in high-speed computing and development of more sophisticated finite element modeling (FEM) software. Traditional package development cycles no longer are efficient for a competitive semiconductor industry that emphasizes a short time-to-market.
With validated computer models, "design of experiments" (DOE) studies of package geometry, material properties and test conditions become more efficient, saving time, cost and manpower. The optimized design is proposed by CAE to shorten the package development cycle. Additionally, CAE is useful for new package validation to evaluate the feasibility of new package concepts without any investment in prototyping and testing.
A thorough package modeling capability should include both package- and board-level modeling, consisting of mechanics of materials, mass and heat transfer, thermodynamics, impact dynamics, and other multi-physics analyses. Commercial finite element modeling software packages are available for detailed static and dynamic parametric modeling.
 Figure 1. The predicted high-stress regions in a smart card module under cyclic pressure test correlates with a crack in an actual unit. |
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Thermo-mechanical Stress Modeling
Linear-elastic stress modeling frequently is applied to analyze the structural reliability of packages. This type of analysis is easy and fast to model, and it is useful when there are time or resource constraints on the project. Sometimes, a more detailed elastic-plastic stress model may be used if the material properties required are available. The models typically are correlated with warpage measurements from moiré interferometry and the predicted failure mode is compared to the results of failure analysis (e.g., cross section). The validated model can identify areas with high-stress concentration that are susceptible to failures. The analysis can be extended with fracture mechanics to analyze die and package cracking, as well as interfacial delamination.
Figure 1 shows an example of a smart card micromodule under pressure test. There is good correlation between modeling and experiment on high-stress regions, distributed along the diagonal of the component. The design can be optimized with a parametric model to minimize package stress.
Viscoelastic Warpage Modeling
Viscoelastic modeling generally is applied for better predictions of package warpage. The analysis is more sophisticated than linear-elastic modeling, and requires time-dependent viscoelastic material properties, especially for mold compound.
One case study examined the warpage in a strip of thin-profile fine-pitch ball grid array (TFBGA) packages. The warpage induced after the post-mold cure process is critical for the TFBGA in this format because it affects the solder ball attach process, and also the subsequent package singulation process. Comprehensive warpage analysis has been performed through experimental warpage measurement, material characterization of mold compound viscoelastic properties, real-time shadow moiré measurements and viscoelastic finite element modeling with parametric studies.1 The 3-D viscoelastic model correlates well with the experimental warpage measurement (Figure 2); therefore, the validated 3-D viscoelastic finite element model with consideration of chemical shrinkage can be used as a reliable tool for BGA warpage prediction.
 Figure 2. Correlation of warpage measurements and different types of modeling. |
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Moisture Diffusion Modeling
Moisture-induced IC package failures, such as popcorning and delamination, are common phenomena during solder reflow. The failures are due to sudden vaporization of moisture absorbed by the package at a high-temperature condition. It is known that package cracking is not controlled by the absolute water weight gain, rather it is because of the local moisture concentration at the critical interface. Therefore, the knowledge of moisture distribution in the package is critical in minimizing moisture-induced failures.
Figure 3 shows the transient moisture distribution in a quad flat no-lead (QFN) package during moisture preconditioning and reflow.2 The moisture diffuses into the package through a mold compound, and it gradually spreads into the die-attach layer. At the end of 168 hours of moisture preconditioning under 85°C/85%RH, the package almost is fully saturated with moisture. The analysis shows good correlation between modeling and experimental moisture weight gain measurement of mold compound material under 85°C/85%RH.
The moisture distribution results can be used as input for further hygroswelling stress modeling and vapor pressure modeling. Moisture diffusion modeling also can be applied to calculate an equivalent moisture preconditioning time for a certain JEDEC level under a different moisture condition. For example, the ceramic leadless chip carrier (CLCC) package should pass JEDEC Level 3 (30°C/60%RH, 192 hours), but the required testing time is too long for sample screening. An accelerated test condition (85°C/85%RH, 50 minutes) was identified as an equivalent by moisture diffusion modeling, allowing a shorter test time.
 Figure 3. Transient moisture distribution in a QFN package. |
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Hygroswelling Modeling
Thermo-mechanical stress is induced by a mismatch of coefficients of thermal expansion (CTE) of a multi-material system. Similarly, hygroswelling or hygro-mechanical stress is due to a coefficient of moisture expansion (CME) mismatch of packaging materials. Polymeric materials expand or swell when moisture is absorbed, and different materials have a unique moisture and hygroswelling material properties.
Figure 4 shows an example of failures in under bump metallization (UBM) in a flip chip BGA after a pressure cooker test.3 The tensile hygroswelling stress along the solder bump/UBM interface is responsible for the failure. The magnitude of hygroswelling stress is of the same order as thermo-mechanical stress.
 Figure 4. UBM failure induced by hygroswelling stress. |
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Vapor Pressure Modeling
The package vapor pressure distribution during reflow is a key factor in understanding the popcorn failure mechanism. A moisture diffusion model is applied to predict the local moisture concentration at the critical interfaces, which then can be used for the subsequent vapor pressure calculations. The vapor pressure modeling applies a micro-mechanics approach, using the representative volume element (RVE) with consideration of the micro-void effect.2,4 High-moisture concentration weakens the critical interfacial adhesion, generates vapor pressure during reflow, and induces hygro-mechanical stress in the package. The vapor pressure saturates much faster than the moisture diffusion. At reflow temperature, the vapor pressure generated can never go beyond the saturated pressure, i.e., a pressure of 2.32 MPa at 220°C. The vapor pressure induces additional mismatch to the package, which is of the same order as the CTE and CME mismatch.
 Figure 5. Strain energy density distribution of TFBGA solder balls. |
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Integrated Stress Modeling
The actual package failure mechanism during reflow is complex, caused by the combined effects of process defects, interfacial adhesion strength, moisture, vapor pressure, thermo-mechanical stress and hygro-mechanical stress. Therefore, there is a need for comprehensive modeling studies on moisture diffusion, thermal effects, hygro-mechanical stress, thermo-mechanical stress and vapor pressure during reflow.
Board-level Solder Joint Reliability Modeling
Board-level solder joint reliability (SJR) is a critical issue during the thermal cycling test for packages such as TFBGAs and QFNs. A typical board-level thermal cycling test requires about two or three months, and the experiment matrix is limited.
Figure 5 shows an example of SJR analysis for a TFBGA package. The fatigue model used is based on modified Darveaux's approach with nonlinear viscoplastic analysis of solder balls. The model includes detailed pad geometry and a realistic shape of solder balls. Temperature-dependent material properties are considered for the BGA packaging materials present. The critical solder ball is observed to be at the diagonal corner. The failure is observed to be along the top solder ball/pad interface, and it correlates well with the region of the maximum strain energy density (SED), calculated by the SJR model.5,6
The model was correlated with six sets of low-profile fine-pitch (LFBGA) and TFBGA thermal cycling data to establish a connection between the SED obtained from the FEA model and the actual characteristic life during the thermal cycling test. Higher SED leads to shorter fatigue life. The FEA is within a ±13 percent error limit of the thermal cycling results. This fatigue life prediction capability gives confidence to users to rely on modeling for board-level SJR evaluation for new TFBGA packages, and to minimize the time consuming and expensive thermal cycling tests.
QFN packages are becoming popular as a low-cost solution for applications with low pin-count requirements. From the failure analysis, it is clear that the peripheral solder joint can crack and propagate through the top interface. The failure mode agrees well with the high SED region predicted by SJR modeling of a QFN.7,8
The solder joint fatigue life calculated by modeling was correlated with eight sets of thermal cycling data of QFN and optical QFN (OQFN) packages, and the correlation was good (within ±34 percent). The parametric modeling studies on package and board geometry, material properties, and thermal cycling test conditions are useful to a package designer in the package development stage.
References
- T.Y. Tee et al., "Warpage Analysis and Viscoelastic Modeling of Block BGA," InterPACK Conference Proceedings, 2001, Doc No. 15726.
- T.Y. Tee and H.S. Ng, "Whole Field Vapor Pressure Modeling of QFN during Reflow with Coupled Hygro-mechanical and Thermo-mechanical Stresses," 52nd ECTC Conference Proceedings, 2002.
- T.Y. Tee et al., "Comprehensive Moisture Diffusion, Hygroswelling and Thermo-mechanical Modeling of FCBGA Package with No-flow Underfill," APACK Conference Proceedings, 2001, pp. 210-216.
- T.Y. Tee, X.J. Fan and T.B. Lim, "Modeling of Whole Field Vapor Pressure during Reflow for Flip Chip BGA and Wire Bond PBGA Packages," 1st EMAP Conference Proceedings, 1999, pp. 38-45.
- T.Y. Tee, K. Sivakumar and A. Do-Bento-Vieira, "Board-level Solder Joint Reliability Modeling of LFBGA Package," 2nd EMAP Conference Proceedings, 2000, pp. 51-54.
- T.Y. Tee, H.S. Ng and S. Pan, "Board-level Solder Joint Reliability Modeling of TFBGA Package," ICEP Conference Proceedings, 2002, pp. 492-497.
- T.Y. Tee et al., "Board-level Solder Joint Reliability Modeling and Testing of QFN Package," ICMAT Conference Proceedings, 2001.
- T.Y. Tee et al., "Comprehensive Design Analysis of QFN and PowerQFN Packages for Enhanced Board-level Solder Joint Reliability," 52nd ECTC Conference Proceedings, 2002.
Tong Yan Tee may be contacted at STMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521; (65) 63507703; Fax: (65) 62598662; E-mail: [email protected].