Wafer-level burn-in with test
05/01/2002
A key enabler for low-cost SoC and SiP
BY GANS GANESAN AND JOHN PITTS
Semiconductor manufacturers are challenged in all market segments to provide products with increased functionality at a low cost. Today, semiconductor packages requiring known good die (KGD), including various types of system in a package (SiP) and multi-chip modules (MCMs), are emerging as alternate solutions. To facilitate these approaches, a test solution is required that delivers fully tested, highly reliable die before module assembly at a low cost. A newly developed direct full-wafer contact wafer-level burn-in with test (WLBT) technology accomplishes this. This approach facilitates cost-effective KGD in wafer form, thus enabling SiP and MCM technology as alternate solutions for the system-on-chip (SoC) approach.
Challenges in Test
While significant opportunities to reduce costs will remain in the front-end through reduced defect densities, aggressive geometric shrinks to reduce die size, and increased wafer size, substantial cost reduction can also be realized in the back-end by properly applying low-cost test methodologies. The increasing complexity of SoC has placed enormous demands on traditional test methods. Simplified parametric-based testing techniques and acceleration methods to increase fault detection, in combination with increased test parallelism, have reduced the unit cost of detecting defective devices while maintaining adequate fault coverage. A more general solution for testing problems is using design for test (DFT) methodology. DFT is being widely adopted for SoC design and now plays a crucial role in reducing new product time-to-market and test cost, while ensuring adequate fault coverage. WLBT technology combines DFT with another essential approach, namely massively parallel testing of a full wafer during burn-in.
 Table 1. Typical defect levels in a Power PC chip at the Sort #1 Unit Probe and WLBT. |
Motorola has various efforts in place to develop and deploy test methods that take advantage of DFT. Working in partnership with Tokyo Electron Limited (TEL) and W.L. Gore and Associates Inc., a production equipment set and full-wafer probe technology have been developed to perform DFT test and burn-in on devices while still in wafer form. Qualification was achieved on a high-performance microprocessor device housed in a flip chip ceramic ball grid array (FC-CBGA) package, demonstrating that the WLBT process can provide reliable wafer-level KGD.
WLBT Deployment Strategy
Figure 1 shows both the standard production flow for a high-performance microprocessor device and the integrated WLBT flow. The first test in the standard production flow is a unit probe process (Sort #1 Unit Probe), in which all devices on the wafer are individually tested for gross defects (opens, shorts, leakage) and screened using both structural (DFT) and functional test patterns. This step provides early speed distribution information and identifies devices with repairable memory arrays. The second test is performed only on die with repaired memory arrays. Using information from both unit probe tests, all "good" units are singulated from the wafer, assembled into a package, and tested in the finished form. Package test consists of two test insertions and burn-in. The initial package test (pre-burn-in) is used to confirm the assembly process (opens and shorts), identify additional device defects, and to finalize the speed grading for the device. Remaining good devices are then processed through burn-in, and fallout is verified with a final post burn-in test.
 Figure 1. a) Standard and b) wafer-level manufacturing flows. |
The goal for integrating WLBT is to ensure the lowest cost, earliest detection of device defects while not impacting upstream or downstream operations or degrading device package reliability. WLBT was inserted into the production flow, replacing Sort #1 Unit Probe. This approach was enabled by the device's "skinny" test interface mode, which minimizes the required test system interface resources and reduces the number of device contacts needed to perform DFT test and stress the part during burn-in. For this philosophy to be successful, a clear understanding of the defect coverage provided by DFT is required. Table 1 shows typical defect levels occurring at the standard Sort #1 Unit Probe step for a microprocessor compliant with the Power PC architecture.
Once inserted into the manufacturing flow, WLBT requires a reconfiguration of the remaining test steps, both to screen those defects that WLBT does not find before assembly, and to eliminate redundant final package tests. All devices that pass WLBT undergo unit probe to capture any defects that were previously undetected or induced at burn-in, verify memory repair, and provide appropriate speed grading. Information from WLBT and unit probe is used to screen as many defects as possible before assembly. Moving burn-in to the wafer level allows for simplification of package test by eliminating both package burn-in and post burn-in test, requiring just a single package test insertion with the possible addition of system-level tests.
Full-wafer Contact Technology
A Z-axis conductive compliant material establishes the full-wafer contact between an interconnect board and the wafer. The wafer is mounted on a vacuum chuck, and a seal ring between the edge of the chuck and the interconnect board allows a vacuum to be created between the wafer and the board. The vacuum compresses the material between the wafer and the board, establishing contact. The full assembly (Figure 2) is referred to as a "contactor assembly."
 Figure 2. Components of a full-wafer contact solution for bumped die products. |
The interconnect board uses seven-layer, high-density interconnect (HDI) technology with a metallic core that matches the thermal expansion coefficient of the wafer under test to minimize the X-Y offset during the test/burn-in at high temperatures. The boards have a total flatness of 25 µm, and are based on the wafer floor plan and pad layout. The interconnect board distributes die contacts to rings of contact pads on the periphery where they are contacted by pogo pins from the WLBT system.
In the first step of the WLBT process, the interconnect board is aligned to the wafer under test (WUT) using a modified TEL prober called a "wafer aligner." Once aligned, the interposer is placed on the WUT and the interconnect board-interposer-wafer-vacuum chuck assembly is created (Figure 2). This assembly is loaded into the burn-in/test chamber in the WLBT system. The temperature of the wafers during burn-in/test is maintained with a closed loop liquid heating and cooling system. A control system maintains wafer temperatures accurately over the full range of power dissipation with a maximum limit of 1200 W. The Gore contactor is currently available for contact to flip chip bumped die only; other contactors exist and are being evaluated for contact to aluminum wire-bond pads. In particular, the TPS probe developed by Matsushita Electric Co. and manufactured by Hoya Co. is reported to be in production.1 Development of full-wafer probes for burn-in requires special attention to the compatibility between the probe and pad/bump metals.
WLBT Manufacturing Demonstration Results
WLBT test results were compared against results from Sort #1 Unit Probe. Figure 3 shows the results of this comparison for a population of 11,000 units from five different production wafer lots. Both Sort #1 Unit Probe and WLBT defect bin results are normalized to the total defect population level as measured at Sort #1 Unit Probe.
DFT detected failures accounted for 75.5 percent of the total defects present in this sample population with 6.5 percent being identified as possible repairable memory array failures. An additional 12.2 percent of defective devices had excessive core current. WLBT achieved 95.4 percent coverage for these defect bins. Of the remaining 12.4 percent failures, 4.8 percent were because of high pin leakage or pin opens/shorts. While these failure modes are not targeted, WLBT detected failures on approximately 75 percent of these samples. The remaining 7.6 percent failures were detected through functional testing.
 Figure 3. A comparison of the test coverage results for Sort #1 Unit Probe and WLBT. |
The second aspect of this comparison looks at the correlation between passing die measured at Sort #1 Unit Probe and WLBT. Successful WLBT deployment requires adequate test coverage as well as assurance that it will not falsely reject good devices. These failures can be either false failures or true failures. Two percent of these failures were isolated to specific WLBT process issues. While not desirable, this level is within the predicted process capability range and is comparable to similar false yield losses observed in unit probe operations. Six percent were possible true device failures, which is consistent with historical fallout on DFT tests at pre-burn-in test in the standard flow. Burn-in effectiveness and package reliability were also demonstrated. The result was that WLBT was as effective as conventional package level burn-in and did not degrade package reliability. Thus, WLBT was qualified in manufacturing using a high performance microprocessor compliant with the Power PC architecture.
Further work is in progress to improve the contact process for C4 flip-chip products and to develop a contact technology for wire-bonded and electroplated bumped products. AP
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Reference
- Y. Nakata et al., "A Wafer-Level Burn-in Technology Using the Contactor Controlled Thermal Expansion," Intl. Conference on Multichip Modules, 1997.
Gans Ganesan, packaging technology manager, networking & computing systems group, and John Pitts, WLBT technology manager, can be contacted at Motorola Inc., Semiconductor Products Sector, 3501 Ed Bluestein Blvd., Austin, TX 78721; 512-933-3640; Fax: 512-993-5562; E-mail: [email protected]; [email protected].