Progress on wafer-level burn-in and test

02/01/2002

AUSTIN, TEXAS - Motorola Semiconductor Products Sector (SPS) has developed and qualified the industry's first wafer-level burn-in and test (WLBT) process for high-performance flip chip microprocessors. WLBT was designed to enable the production of reliable known good die (KGD) for use in applications such as direct chip attach systems, multi-chip modules, systems-in-packages, stacked-die assemblies and wafer-level KGD. These module applications represent an emerging market that is targeted for 50-percent annual growth, according to analysts.

Motorola has provided volume production of wafer-level burn-in KGD for several years, primarily to the automotive industry. According to the company, Motorola plans to use its expertise in KGD technologies to provide the capability of combining logic, flash memory, SRAM or DRAM into a single flip chip module or package in some of its networking and communications product offerings.

A few years ago, Motorola started working with Tokyo Electron Ltd. (TEL) and W.L. Gore & Associates Inc. to develop a direct contact WLBT system. Process qualification was achieved on Motorola's flip chip ceramic ball grid array device compliant with the PowerPC instruction set architecture. Production-capable equipment and processes have been installed and characterized in Motorola's final manufacturing facility in Austin, Texas.

Motorola and TEL plan to continue their development relationship to produce solutions for wirebond devices. According to John Pitts, WLBT technology manager, these solutions should be available by mid 2002.