In the News
10/01/2003
Entegris Adds Partners to Wafer Handling Initiative
CHASKA, MINN. — Entegris Inc. added eight new partners to the Entegris Ultra-Thin Wafer Partner Program. The program is a non-exclusive open alliance to support thin silicon wafer handling in the semiconductor industry. Under terms of the agreement, the companies will join forces to promote integrated solutions for semiconductor wafer thinning and stress removal, along with advanced techniques for thin wafer handling and transport. The alliance also calls for all companies to engage in joint marketing initiatives.
Current global partners of the program include ESEC, PROTEC group AG, Integrated Dynamics Engineering, Silicon Quest International, Dymatix Automation Systems, SEZ Group, Teikoku Taping Systems Co. Ltd. and Carinthian Tech Research AG. Tru-Si, a high-technology wafer thinning and handling equipment company, has been involved in the program since September 2002.
The purpose of the Ultra-Thin Wafer Partner Program is to demonstrate compatibility between high-performance wafer thinning equipment, processes and thin wafer handling, and transport systems.
The program was formed to address wafer integrity, handling and transport issues by bringing together industry leaders to share their expertise and deliver best-of-breed solutions to the industry — solutions that are key to protect thin and fragile silicon wafers from contamination and breakage throughout the semiconductor manufacturing process.
Amkor Unveils Packaging Technology Roadmap
CHANDLER, ARIZ. — According to Amkor Technology, in order for semiconductor companies to accommodate technology roadmap requirements and meet demand for advanced semiconductor chips with greater functionality, a trend toward greater collaboration between device makers and their packaging technology partners is becoming standard.
In keeping with its 35-year history of enabling advances in semiconductor technology to reach the system level, the company unveiled its most comprehensive packaging technology roadmap, featuring a spectrum of solutions that include advances in CSPs, high-performance packaging and system-in-package (SiP) technologies. The roadmap also reflects an increasingly complex packaging environment for ICs used in high-growth applications such as broadband, home networking, digital imaging and gaming, in which size, functionality and cost are critical factors that drive adoption rates.
In unveiling the roadmap, Amkor cited flip chip packaging, stacked packaging, SiP, CMOS image sensors and MEMS as growth areas supported by significant investment in package development in recent years. In regard to flip chip packages, the roadmap illustrates both current and future advances for these packages, which provide superior electrical connectivity, increased speed and require lower voltage than wire bond packages. The company has seen strong demand for flip chip solutions for power management, PLD and ASIC applications, and expects to see a migration from wire bond to flip chip packaging by graphics and chipset suppliers. Worldwide flip chip demand grew considerably from 2000 to 2002, and is expected to surge over the next several years as substrate costs are reduced.
Universal Pursues Price Initiative Goal
BINGHAMTON, N.Y. — Universal Instruments Corp. (UIC) embarked on a global cost reduction initiative to set new product pricing standards in the assembly industry.
The company is implementing a price reduction strategy across the board for its surface mount products and standardizing global pricing. The move is facilitated by the corporation's strategy of cost reduction in every part of its operation and driven by the stated goal of becoming the No.1 global solutions supplier in the industry with the lowest costs and highest earnings growth.
Key to the new pricing structure is the policy to pass on the dividends of cost reductions Universal has secured on four fronts: new manufacturing operations in China coming online; globalization of the supply chain; driving costs out of the U.S. supply base; and operational consolidation into state-of-the-art premises in greater Binghamton, N.Y. Additionally, design engineers have attacked cost at the outset of recent development projects — the results being evident in the company's new mid-range AdVantis products.
In other Universal news, the company has established Dover Software India (DSI) in Bangalore. DSI is a cooperative arrangement between Dover companies UIC and DEK International to establish a software engineering organization in India.
Peter Bollinger is the manager — system software products and India operations. This comes in addition to his existing responsibilities with Dimensions, the company's software product line. Bollinger has been key in establishing the DSI facility and staffing.
Ketan Parekh is president of DSI. He is responsible for all business and software development operations within DSI. He is accountable to both DEK and UIC for product delivery and development.
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DuPont Electronic Technologies Creates New Business
RESEARCH TRIANGLE PARK, N.C. — DuPont Electronic Technologies formed a new business unit, DuPont Integrated Circuit (IC) Fabrication Materials. The new business is part of DuPont Electronic Technologies' strategy to extend its leadership position in circuit materials into advanced materials for ICs. Jerry Coder has been named president, DuPont IC Fabrication Materials.
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Coder, formerly president of DuPont EKC Technology, brings industry experience to the new business unit. He will be responsible for driving strategy, managing the network of businesses currently serving the IC industry and directing growth into new areas that leverage DuPont materials technology.
DuPont Electronic Technologies' strategy is to exploit the synergies between its existing IC fabrication materials business and R&D programs to create an expanded portfolio of highly engineered and differentiated materials for advanced IC manufacturing.
Coder will be based at DuPont EKC Technology headquarters in Danville, Calif. John Odom, former business manager of DuPont Printed Circuit Materials Americas, will become president of DuPont EKC Technology.
K&S Sells Saws, Hard Material Blades Business
WILLOW GROVE, PA. — Kulicke & Soffa Industries Inc. signed an agreement of sale for the assets associated with the company's sawing equipment and hard material blades operations. The agreement includes fixed assets, inventories and intellectual property for the company's sawing equipment business, located in Haifa, Israel, and the Micro-Swiss hard materials blades business, located in Yokneam, Israel.
Completion of the sale is subject to certain conditions, including approval of the K&S Board of Directors, completion of an IT transition support agreement, approval of Israeli government agencies and the consent of various third parties. The company, however, does not intend to sell its Semitec brand, IC dicing blades business, located in Santa Clara, Calif.
These businesses represent approximately 2 percent of the company's revenue for the first three fiscal quarters, so K&S' shareholders did not see a significant shift in revenue going forward as a result of the sale. However, the company expects to realize further cost reductions as a result of this sale.
Amkor Aligns with UTAC
CHANDLER, ARIZ. — In keeping with its strategy of becoming a leading provider of turnkey semiconductor assembly and test services for the emerging Chinese chip industry, Amkor Technology Inc. entered into a business alliance with United Test and Assembly Center Ltd. (UTAC). The alliance combines the strengths of both companies to create a turnkey assembly and test supplier capable of supporting the local Chinese wafer foundries as well as IDMs looking to service their end customers in the China market.
As part of the alliance, UTAC Co. Ltd. is entering into a multi-year lease agreement to locate its China test center within Amkor's existing factory in the Waigaoqiao Free Trade Zone in Shanghai. The test center will be equipped with multiple test platforms, including the Agilent 93K, Teradyne J750 and Advantest 5581. These test platforms will be suitable for testing a range of device technologies. The center will provide a range of test services, including wafer probe, burn in, final test and all related back-end services.
New Company Offers Flip Chip Technologies
BILLERICA, MASS. — Polymer Assembly Technology (PAT), a new company founded by industry veteran Jim Clayton, opened its doors to offer leading-edge flip chip technology featuring high-density, low-temperature processing through the use of polymer conductive adhesives. The company's founder and president previously was the director of R&D at Polymer Flip Chip Corp. and brings more than 30 years of experience in microelectronics assembly and packaging to the new position.
The company provides an alternative to traditional solder flip chip assembly by using electrically conductive and non-conductive inks that can be stencil printed and cured at temperatures as low as 80°C. This alternative flip chip technology is timely because new no-lead solder alloys are pushing processing temperatures higher than 250°C, placing additional strain on fragile components.
PAT also is involved in prototype development and low-volume assembly of high-density compound semiconductor devices. Cd/Zn/Te detectors, for example, currently are being developed for several medical and astronomical X-ray imaging applications. These detectors contain large numbers of contacts — some in excess of 1,000 — and cannot be exposed to temperatures above 90°C without altering their performance. Therefore, a low-temperature flip chip solution is needed to assemble these devices. The company has developed precision techniques for depositing silver-filled conductive bumps on these types of components and then assembling them at temperatures of 80°C.
Additionally, the company has developed a unique expertise that combines adhesive-bumped sensor devices with gold stud bumped VLSI chips. Advancements in Au-wire ball bumping technology now enable multi-stacked stud bumps that can reach 100 µm in height with ±5 µm uniformity. When combined with PAT's precision polymer bumping process, connection density reportedly can achieve 125 µm pitch, yet still control epoxy spreading sufficiently to prevent electrical shorts or epoxy contact on the opposite surface. Once cured, conductive epoxy will not wick between pads if exposed to subsequent high thermal processing.
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Semiconductor Factory Automation Growth Expected
NEW TRIPOLI, PA. — Factory automation tools, which dropped 8 percent in 2002, will fully recover in 2003 with a 15 percent increase, according to the report "Semiconductor Factory Automation: Technology Issues And Market Forecasts," recently published by The Information Network.
The market for carrier transport systems — including interbay and intrabay equipment and WIP storage — had Daifuku with a 28 percent share in 2002, ahead of other key companies.
According to the company, the carrier transport is extremely volatile. That market dropped 50 percent in 1998 and increased only 6 percent in 1999, significantly less than the equipment and IC markets. Growth in 2000 was 80 percent. In 2002, the market dropped 8 percent while the entire front-end semiconductor market dropped 26 percent.
Significant under-investment since 2000 forces an upgrade cycle even when there is an absence of robust economic activity. This will equate to 15 percent growth in 2003 and 26 percent growth in 2004.
INCEP Announces Power Delivery Technology, HP Agreement
SAN DIEGO, CALIF. — INCEP Technologies signed an agreement with HP to develop power delivery technologies for use in high-performance systems that use Itanium microprocessors, including HP's Integrity enterprise servers.
INCEP is establishing a new standard with its microprocessor power delivery architecture, which combines the microprocessor die and its chip-carrier substrates with the microprocessor's power conditioning circuitry. The solution requires only a single heat dissipating device and retention solution for the co-packaged microprocessor and power supply. INCEP has developed a patented approach of applying power to the surface of a microprocessor package, which supports traditional pin grid array as well as land grid array configurations. The solution also requires a high-performance power connector and a high-density DC/DC converter, which combine to deliver the necessary device power. This assembly is the ZVRM assembly for computing applications, and the Zbrick assembly for communication applications.
High-density power and thermal solutions are expected to be a key differentiator in systems that feature Z-axis power technologies. Under the terms of the agreement, INCEP has made its innovations in power delivery available to HP for multi-processor power modules, and will be working with HP over the next three years on enterprise server microprocessor power delivery applications.
Sonoscan Expands Component Screening Program
ELK GROVE VILLAGE, IL. — Sonoscan Inc. expanded its component-screening program to include large lots of components, including advanced small-form components such as BGAs, microBGAs and CSPs.
The Hi-Rel Acoustic Screening program is a service of the company's applications and testing laboratory. Acoustic microimaging historically has been used to screen relatively small quantities of components, but the expanded program targets volumes from 10,000 to 250,000 units.
The program's purpose is to identify and remove components with internal packaging defects that later may become electrical defects. Electrical tests performed by manufacturers cannot find these defects, which are capable of initiating massive field failures.
Performed in Sonoscan's applications laboratory, the expanded program uses the company's C-Mode scanning acoustic microscope (C-SAM) and Fast Automated C-SAM tray scanning System (FACTS2) to enable fast turnaround. Components are imaged in JEDEC-style trays. Because only good components survive the screening program, manufacturers can continue production without running unacceptable failure risk.
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UB Materials Engineer Invents New Thermal Paste
BUFFALO, N.Y. — A materials engineer at the University of Buffalo invented a new thermal paste that will help solve the issue of overheating in high-performance personal computers and other electronics.
Created by Deborah D.L. Chung, Niagara Mohawk professor of materials research in the UB School of Engineering and Applied Sciences, the paste, when applied between a heat sink and a heat source, can improve the conduction of heat from the heat source to the heat sink. Heat sinks are used in electronics to draw heat produced by the device away and prevent it from overheating.