Power IC Packaging Improves Performance, Functionality
10/01/2003
PQFN LEVELS FIELD BETWEEN SILICON AND PACKAGE.
By Clem Brown and Russell Shumway
In most semiconductor technologies, the silicon is outpacing available packages' ability to provide the full advantages. Power ICs are no exception and, in fact, are behind silicon capabilities. A new packaging technique promises to change this situation. One power quad flat-pack no-lead (PQFN) package technology* provides additional pin-out, isolation for multiple die, improved thermal performance, high manufacturability and flexibility for new designs within a common surface-mount form factor. This article compares the PQFN package to an earlier quad flat package and an existing power integrated circuit (IC) package.
Establishing an IC Package
For power ICs, technical requirements include the ability to handle high currents, high power dissipation and multiple die. The heat slug outline package (HSOP) is available in a number of pin outs, and its single-attachment flag design means that products having multiple die are difficult to isolate electrically from each other, limiting silicon design and system architectures. With external leads extending peripherally from the package, the HSOP package area efficiency is not optimal for the newest printed circuit board (PCB) layouts. Another packaging format, the quad flat no-lead (QFN), inherently is more efficient in surface area but limited in power dissipation capability. The QFN's limited power capability is due primarily to its relatively thin leadframe and epoxy die-attach material. Standard QFNs for automotive applications include: 32-lead, 7 ¥ 7 mm (0.65 mm lead pitch) and 44-lead, 9 ¥ 9 mm (0.65 mm lead pitch) exposed pad options. The QFN package was used as a starting point to develop an improved power IC package.
The power package combines the attributes of older and larger HSOP power packages with the surface efficiency of the newer QFN package. The PQFN is also available in either custom multi-die solutions or standard, single die solutions using the same packaging technology. A custom PQFN package is shown in Figure 1.
 Figure 1. Cross-section of PQFN package, showing isolated die flags, gold and heavy-gauge aluminum wirebonds. |
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The mold array packaging (MAP) process steps are similar to those of the QFN except for modifications required with the addition of solder paste die attachment and large-gauge wirebonding. Singulation is performed by a saw process to the molded array, leaving vertical edges on the body of the PQFN.
PQFNs provide a multi-chip solution in a single package. The MAP process allows physical flag isolation, as well as design and process flexibility. The PQFN has superior thermal performance (Rth-JC<1°C/W) with 20-mil-thick copper leadframe and solder die-attach. The chemical etch leadframe fabrication process naturally forms mold-locking features that have increased moisture ingress paths and have allowed the package to achieve moisture sensitivity level (MSL) 3 at 260°C, as defined by Joint Electronic Devices Engineering Council (JEDEC) J-STD-020 industry testing standards. The small footprint provides a cost-effective and area-efficient solution for multi-chip power IC products. Some of the isolated pad layouts that have already been developed are shown in Figure 2.
 Figure 2. Custom configurations for the PQFN. |
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A comparison to an earlier quad flat package (QFN) and the HSOP power package shows the improvements that the PQFN package provides. Figure 3 shows the physical layout size differences between the packages.
 Figure 3. Mounting side with exposed heatsink area of HSOP compared to QFN and PQFN package. |
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The QFN was designed to handle a single die with moderately high pin counts. In contrast, the unique leadframe etching process developed for custom PQFN designs allows formation of isolated die-attach flags. In addition, the PQFN accommodates large-diameter wedge bonding for higher current carrying capability and to reduce packaging-related on-resistance. The PQFN uses 20 mil Cu leadframe material versus 5 to 8 mil thickness commonly used in the QFN. The body thickness of the PQFN was increased to a 2.1-mm-thick body versus 1.0 mm for the QFN to accommodate the thicker leadframe and larger diameter wire loops. The PQFN's terminal lead thickness and width also exceeds the HSOP. Both the PQFN and HSOP use solder die-attach. The QFN uses epoxy die-attach material with inherently reduced thermal capabilities. Thicker leadframe and solder die-attach reduces thermal resistance and allows higher power dissipation capability in both transient and steady-state conditions. Custom versions can use higher current carrying aluminum wires and either gold or aluminum signal wires. The lead pitch of the PQFN standard platform is 0.8 mm. Custom platform designs have application-specific lead sizes.
The HSOP package provides an industry-standard power IC package with good thermal capability and a higher pin count than previous power IC packages. It was designed to accommodate a single die or die that could be mounted on a common substrate. The area efficiency of a package is limited at the highest level by the body area-to-footprint ratio. This ratio is 176/231.2 = 76 percent for the 20-lead HSOP. In contrast, both the PQFN and the QFN have a 100 percent rating.
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One of the keys for improved thermal resistance, lower on-resistance and higher power capability is the use of a solder die attachment. This is an integral part of the PQFN.
Power dissipation and resulting thermal capability shown in Table 1 are based on the PQFN mounted on FR-4 circuit board with two layers of 2 oz copper. Using thicker copper, dual-sided surfaces thermally coupled together or a metal-backed board can improve package performance. The PQFN provides an affordable automotive package primarily due to its high manufacturability. The PQFN uses the same basic manufacturing scheme and construction as the QFN, and as a result, the comparative cost of the PQFN is less than that of the existing HSOP industry-standard power IC package.
Packaging Reliability
Solder joint board-level reliability (SJR) can make or break a new package platform without peripheral leads to buffer cycling stresses. Extensive thermal and finite element model simulations have shown that solder reliability is extremely robust with projections of more than 7,000 thermal cycles (-65°C to 150°C) from circuit board mount studies. The 16-lead custom PQFN package has demonstrated more than 3,200 cycles in empirical qualification testing, with customers normally requiring a maximum of 2,000 cycles capability to the first measured solder joint failure. Expectations for standard PQFN packages extend to 7,200 cycles. Results indicate that the solder joints with highest strain rates are those at the corner of the package. These solder joints have the most strain at the pad backside beneath the package, not at the solder fillet located on the exterior base edge of the packages. The PQFN's large exposed pads see little to no strain during temperature cycling and improve board-level reliability.
The solder joint modeling enabled the rapid design improvements in this and many other package development projects. Comparison of the model with extensive empirical data from existing packages helps establish the correlation and every usage of the tool has continued to verify its validity.
IPC/JEDEC defined MSL classification testing J-STD-020 to rate surface mount devices' sensitivity to moisture-induced stress. This is done so various packages can be properly packaged for shipping, stored and handled to avoid thermo-mechanical damage during assembly solder reflow attachment and/or repair operations. MSL for surface mount parts requires preconditioning that allows moisture to enter the package. In addition, three solder reflow assembly cycles are performed to match conditions that could occur in a customer's board assembly. A 12-mm custom PQFN has achieved MSL Level 3 at 260°C elevated reflow temperature compatible with environmentally preferred, Pb-free, SMT mounting processes. The PQFN achieved MSL Level 1 at 220°C peak reflow temperature compatible with most SnPb SMT processes. Level 1 means the PQFN does not require dry packing for shipping or any special handling restrictions after the shipping bag container is opened.
Next Level of Power Control
A custom application PQFN can have four or more different silicon or GaAs die and electrically isolate all the flags. The fact that the dice are physically isolated from each other opens several new design possibilities, providing both silicon and packaging engineers flexibility for future designs. In addition, since the capability of many existing power ICs exceeds the capability of previous packaging, the PQFN package provides an opportunity for performance improvement for existing silicon designs. For example, a single-motor driver designed for a 9 ¥ 9 mm2 QFN package can become a dual-motor driven in the PQFN package without any loss in performance and the ability to more than double the power dissipation. Also, the combination of existing control die with a variety of existing power metal oxide semiconductor field effect transistor (MOSFET) die can produce an application-specific solution quickly.
*PQFN package technology by Motorola.
CLEM BROWN is the manager of power packaging development at Motorola's Semiconductor Products Sector and can be reached at [email protected]. RUSSELL SHUMWAY is the manufacturing program manager with Motorola's analog products division and may be reached at [email protected].