Mapping and Traceability Minimize Recall Costs
06/01/2003
By Dave Huntley
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Manufacturing industry's pressing need for open systems standards for traceability is motivating new developments in standards for test assembly and packaging.
Today, manufacturers operate in a climate of unprecedented accountability and liability. A defective component that produces product failure can have ruinous consequences for manufacturing. Even when many units are fault-free, compliance with regulatory and product liability requirements often necessitates their recall and examination.
Product recalls are time-consuming and costly. Direct costs — investigation of product failure, notification to customers and repair or replacement of defective product or component — often run to hundreds of millions of dollars. Indirect costs — negative publicity, loss of sales and impact on market value — can be much higher. For example, when Intel announced the recall of close to one million flawed motherboards in May 2000, the news wiped nine percent off the corporation's stock price.
To determine the cause of the defect and subsequent course of action, manufacturers must have the data necessary to ascertain which specific products were built using the defective component or process. This mandates traceability extending right down to wafer level.
SEMI standards T1 through T11 deal with marking wafers, boxes, flat panels and metal lead-frame strips (T9) with a 2D data matrix code. The Traceability Committee in the SEMI Standards Program is now working on a proposal for a standard for marking individual devices, Wafer-Level Back Surface Marking (SEMI Doc #3263). Since the device may be small, the mark must also be small. Fortunately, the 2D matrix format contains densely packed data, and it is expected that a 22 x 22 2D matrix code will fit on the majority of devices and such a code can represent 43 characters of data. The proposal for the contents of that code is based on a standard from Automotive Industry Action Group (AIAG) for Parts Identification and Tracking. The AIAG standard defines three fields, a product code, supplier code and a traceability code.
The traceability code should be able to uniquely identify a singulated part in the field and trace its history back through the manufacturing process. SEMI M12 defines the traceability code for a wafer as 8 characters. Assuming that is sufficient to uniquely identify wafers, then another 4 characters can uniquely identify the device within the wafer. That allows up to 364 or 1,679,616 devices per wafer.
The next problem is how the laser marking equipment should report the data marked on the device to the host so that it can be stored in the database. A new proposal, Device Tracking Data (SEMI Doc #3754), specifies how a map of device mark information (device ID data) for a strip can be uploaded.
Devices may be marked while still part of a wafer, on the backside of the wafer. They may also be marked when they have been transferred to a strip. The device ID data can be correlated to the coordinates on the strip, but there is still the question of which coordinates on which wafer that device came from. SEMI Doc #3754 also contains a specification of device tracking data. This defines how any equipment that transfers devices from one substrate to another (e.g., wafer to strip) can report the "from" and "to" information for each device.
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So far, we have dealt with uniform 2D arrays of devices on substrate to which we assign corresponding 2D arrays of data — BinCode maps, device ID maps, device tracking maps. This covers much of today's device manufacturing requirements, but the packaging of multiple devices together to form a composite device is becoming more and more prevalent (e.g., stacked devices, multi-chip modules, etc.). For such devices it is necessary to identify whether the map relates to the composite device or one of its components, and if to a component, then which one? The proposed solution to this problem is the substrate layout data also described in SEMI Doc #3754. This describes the geometry of the substrate in the X, Y and Z directions.
The substrate layout contains one or more top-level layouts, for example, the 2D matrix code layout, the fiducial mark layout and the device layout. The 2D matrix code layout defines exactly where the 2D matrix code will be printed and how big it is. The fiducial layout defines exactly where the fiducial marks used for alignment will be printed and how big they are. The device layout defines exactly where the device array starts, how many rows and columns it has, the device size and the step distance between repeating patterns. Each of these layouts may contain a picture of what one element of that layout looks like. This may be used by the operator to verify orientation, or by the equipment to compare with the actual image on each substrate it processes.
Each layout may have other layouts nested within it. So the top-level device layout might have a layout within it that defines how the individual devices within the composite device are arranged. All layouts are in 2D arrays of elements, so the individual device layout can be expanded according to its parent composite device layout to form a 2D array for the whole substrate. Each individual device on a substrate of composite devices can, therefore, be uniquely identified by X and Y coordinates.
Each layout with a substrate has a unique name that can be referred to by the BinCode maps, device ID maps, and device tracking maps. The X and Y coordinated in the map correspond to the X and Y coordinates of the layout expanded up to the top-level layout for that substrate.
Once SEMI Doc #3754 is approved, it will be possible to take a failed composite device in, say, an automobile, and from its 2D matrix mark identify the vendor, the exact strip it came from, and the coordinates on that strip. It will further be possible to trace back to the wafers where each of the individual devices within the composite device came from, and the coordinates on that wafer. With implementation of the already approved SEMI E90 Substrate Tracking standard, it will be possible to determine when the strip and wafers were processed and the equipment used.
Dave Huntley, president, can be contacted at Kinesys Software Inc., 6 C Street, Petaluma, Calif. 94952; (707) 766-8855; Fax: (707) 766-8196; E-mail: [email protected].