Board-level Reliability Design
06/01/2003
Analysis of three types of 0.5 mm pitch CSPs
By Tong Yan Tee
A chip scale package (CSP) is defined as any IC package with an area less than 1.5x in die area, a package width less than 1.2x in die width, or any fine-pitch (0.5 mm or less) area-array package. Product manufacturers typically are concerned about board-level solder joint reliability of CSPs during thermal cycling tests. The typical thermal cycling condition required is -40° to 125°C to ensure reliable package performance under extreme operating conditions.
The process of thermal cycle testing is time consuming and costly. Therefore, finite element analysis (FEA) modeling is used widely as an analysis tool for solder joint reliability, especially during the design stage of new packages because of recent advances in high-speed computers and the development of more sophisticated finite element models. Researchers use many approaches in the modeling of fatigue life, e.g., stress-based, plastic/creep-based, energy-based and damage accumulation-based models. Darveaux methodology is a common approach used in fatigue modeling that applies both energy and damage accumulation-based theories. A life prediction accuracy of ±2x generally is considered adequate due to the complex nature of solder material's creep behavior, and also uncertainty in the board-level thermal cycling test.
 Figure 1. Schematic of QFN-8 x 8 mm. |
null
In this article, modeling and testing of three types of 0.5 mm pitch CSPs are analyzed: thin-profile fine-pitch BGA (TFBGA), quad flat non-lead (QFN) and wafer-level CSP (WL-CSP). A TFBGA 7 x 7 mm studied has 108 I/O, thin substrate of 0.22 mm, 0.6 mm mold compound thickness and can be assembled in matrix form to save costs. Alternatively, QFNs — types of leadframe CSP — are gaining popularity as low-cost solutions for applications with low pin-count requirements. A QFN 8 x 8 mm with 52 leads is studied in Figure 1. WL-CSP is a real CSP (package size same as chip size), and this wafer-level package can be mounted directly to the board using flip chip technology. The staggered array with 18 I/O allows more solder bumps to fit under the same die area (Figure 2).
 Figure 2. Schematic of WL-CSP with staggered array. |
null
Complete board-level solder joint reliability comprises the thermal cycling test, drop test, vibration test, bending test, etc. TFBGA, for example, has a different failure mode and mechanism under thermal cycling and drop test. Design engineers must compromise on various board-level design constraints and customer requirements. The recommendations given here are based only on the thermal cycle testing.
Solder Joint Fatigue Model
Both global and local full 3-D FEA models are constructed for TFBGA (Figure 3) and WL-CSP to predict the fatigue life of solder joint during the thermal cycling test. As for QFN, a 3-D sliced model is applied (Figure 4), in which only one row of lead with solder is simulated to reduce computation time. Compared to the full 3-D model, the accuracy of the sliced model is acceptable, and both models give the same trend of results, which is useful for relative comparison of solder joint fatigue life. Temperature-dependent material properties are considered for the package materials used. For solder material, Anand's model is applied to describe the creep behavior. The rest of the materials are assumed to be linear elastic, and the board is considered to be orthotropic.
 Figure 3. Global/local model approach. |
null
 Figure 4. 3D sliced model for QFN. |
null
For typical solder materials, creep is the dominant process during thermal cycling condition. Steady-state creep of solder can be expressed by a constitutive equation in the form of
 |
null
where
 |
null
is the steady state strain rate, k is the Boltzmann's constant, T is the absolute temperature, σ is the applied stress, Qa is the apparent activation energy, n is the stress exponent, α is the stress level at which the power law dependence breaks down and Css is a constant.
Darveaux's approach applies Anand's model of ANSYS to calculate the average strain energy density (SED) per cycle accumulated along the critical failure interface. The critical solder joints for TFBGA and WL-CSP are observed to be at the outermost diagonal corner because of strong distance-to-neutral-point (DNP) effect. The failure interface is along the top solder/pad, matching well with the maximum SED observed by modeling (Figure 3). As for QFN, the top peripheral solder and lead interface is the most critical. There also is good correlation between modeling and failure analysis. Larger SED leads to shorter solder joint fatigue life.
The SED obtained from the viscoplastic modeling then can be related to compute the characteristic life:
 |
null
where η is the fatigue life at 63.2 percent failure rate, C1 and C2 are the correlation constants, and a is the length of critical interface (e.g., solder mask or UBM opening size). This modified approach does not consider the crack initiation life, and assumes that the crack propagation life is dominant. This assumption is supported by good FEA-thermal cycling correlation. There are no universal correlation constants because these values depend on the type of packages and finite element model constructed. Because the original constants published by Darveaux were derived for certain BGA packages, there is a need to modify the constants for application in other package types. The constants can be curve-fitted from correlation of FEA and thermal cycling test data to minimize the errors induced during board assembly, testing and modeling. The same constants then can be applied confidently for further design analysis. This approach is more accurate than using the original Darveaux constants.
FEA-thermal Cycling Correlation
Board-level thermal cycling tests were performed on a TFBGA, QFN and WL-CSP. A test board with daisy-chain routing monitored the resistance change that resulted from solder joint failure. A resistance reading above 300W is considered a failure by the event detector, a real-time resistance monitoring system. The test standard followed was JESD22-A104-B, and thermal profile of -40° to 125°C (40 min/cycle) was applied.
The cycles to failure, Weibull plots of these CSPs, can be obtained from thermal cycling tests. The Weibull equation can be described fully with the availability of two Weibull parameters, β and η, by
 |
null
where N is the solder ball fatigue life at corresponding failure rate (F), β is the slope of Weibull plot and h is the characteristic life at 63.2 percent failure rate, which can be correlated directly with FEA predicted fatigue life, computed from SED per cycle.
Correlation constants (C1 and C2) in the second equation are iterated such that the fatigue life differences between modeling and experiment data are minimized using the least square fit method. The FEA-thermal cycling correlation for TFBGA is within ±13 percent difference. As for the QFN, the error is within ±34 percent, which is better than the ±2X error acceptable by Darveaux. For WL-CSP, only one set of thermal cycling test results is available; therefore, the correlation constants are modified from the closer TFBGA package group. Similarly modified constants are applied throughout the rest of the parametric studies of package and board geometry to obtain a consistent relative comparison of solder joint fatigue life.
CSP Design Analyses
The validated CSP fatigue models are applied for parametric studies of five common effects: die size, die thickness, solder joint standoff, solder pad opening size and board thickness. For parametric studies, one design variable will be changed at a time with respect to the control case, and percentage of difference is calculated as shown in the table.
Effect of Die Size. The three CSP types with smaller die size have longer fatigue life. For TFBGA and QFN with smaller die, the die edge is farther from the critical solder joint, resulting in less local coefficient of thermal expansion (CTE) mismatch. As for WL-CSP, smaller die results in shorter DNP and, therefore, lower SED and longer fatigue life. Typically, various die sizes may be chosen for the same package and die pad size, depending on the application. It is important to understand the sensitivity of this die size range on fatigue life.
Effect of Die Thickness. All CSPs studied have better solder joint performance with thinner die. For QFN-8 x 8 mm, fatigue life is increased by 23 percent when die thickness is reduced from 0.38 to 0.25 mm because there is less local CTE mismatch between die and solder joint. A similar trend of this effect also is observed in actual thermal cycling tests. Thinner die implies more mold compound material (higher CTE than die), resulting in a higher package mean CTE and less global CTE mismatch with the FR4 board (higher CTE than average package materials). It has been found that a higher package mean CTE (e.g., higher mold compound CTE) enhances the solder joint reliability for TFBGA and QFN.
Effect of Solder Joint Standoff. All three types of CSPs have longer fatigue life with higher solder joint standoff. The larger separation distance of solder helps reduce the shear strain induced during thermal cycling. For the WL-CSP studied, the fatigue life is improved by 17 percent when solder joint standoff is increased from 0.25 to 0.30 mm. For TFBGA and WL-CSP, because of constant solder volume, higher solder ball standoff usually results in smaller maximum solder ball diameter, which also helps enhance the fatigue life.
 Table 1. Summary of design analyses for 0.5 mm pitch CSPs: TFBGA, QFN and WL-CSP. |
null
Effect of Solder Pad Opening Size. TFBGAs with larger solder mask opening size, QFNs with longer peripheral lead length and WL-CSPs with larger UBM opening size have longer fatigue lives because of longer critical solder/pad interfacial length. According to the second equation, the crack requires a longer time to propagate through the failure interface. For the TFBGA-108 studied, the fatigue life can be enhanced by 56 percent when the solder mask opening size is increased from 0.27 to 0.35 mm. This effect is significant; however, the solder standoff typically will be lowered with larger wetting areas and lower fatigue life. There is a need to compromise between the values of solder joint standoff and pad opening size. Modeling can be applied in such design optimization.
Effect of Board Thickness. For the CSPs investigated, thinner boards result in better solder joint reliability, especially for QFN and TFBGA. This is because the FR4 board has a larger CTE than package mean CTE. Thinner boards help reduce global CTE mismatch between the package and the board. For WL-CSP, board thickness is not a concern. Instead, the board in-plane CTE is critical and lower values are preferred.
Conclusion
Detailed solder joint fatigue models with life prediction capability are established for three types of CSPs. Modified Darveaux's approach is applied with unique correlation constants for TFBGA, QFN and WL-CSP package families.
The correlation between modeling and thermal cycling test is good. The relative fatigue life predictions are consistent with typical experimental observations. Generally, for enhanced solder joint reliability of CSPs, it is recommended to choose smaller die size, thinner die, higher solder joint standoff, bigger solder pad opening size and thinner boards.
Fatigue modeling can be applied for design analysis of solder joint reliability to save cost, time and manpower in performing the DOE studies by thermal cycling tests. This is especially useful for new package development. Fatigue modeling also can be integrated with electrical simulation and thermal analysis for a complete board-level reliability design solution.
References
For a complete list of references, please contact the author.
TONG YAN TEE, lead R&D engineer and CAE team leader, may be contacted at STMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, (65) 63507703; Fax: (65) 62598662; E-mail: [email protected].