Cover Story: Flip Chip and BGA Solder Joint Reliability
05/01/2003
Applying the Moiré Interferometry technique
BY HUA YE, CEMAL BASARAN, DOUG HOPKINS, HENG LIU and ALEXANDER CARTWRIGHT
The trend in flip chip and ball grid array (BGA) packages to increase I/O counts drive the interconnecting solder joints to be smaller in size and, thus, have higher current density. The current densities will increase further as chip voltage decreases and absolute current levels increase. The same trend in current densities in interconnecting solder joints also is occurring in flip chip power semiconductors and evolving system-on-package power processors.1,2 A physical limit to increasing current density in both microelectronics and power electronics is electromigration. Electromigration of interconnect metal lines is the major failure phenomenon in integrated circuits (IC), but until recently it was seldom recognized as a reliability concern for solder joints. Most research had focused on electromigration of thin metal lines, and little on solder interconnects.3-8
The ultimate goal of this research project is to develop a constitutive model to predict the stress-strain field in a solder joint under electrical current stressing so that it can predict solder joint reliability finite element (FE) simulation. The Moiré interferometry technique is used to measure the in-situ strain field evolution in the BGA solder balls under current stressing. To observe the microstructural and mechanical property evolution, flip chip solder joints were stressed at very high-current density and measured using scanning electron microscopy (SEM), energy dissipation X-ray spectrum (EDX) and nanoindentation techniques.
Moiré Interferometry Technique Experiments
The Moiré interferometry technique developed at the Electronic Packaging Lab at SUNY Buffalo is capable of measuring small displacement with a resolution of 0.04 µm. Two copper plates were used as substrates to build the BGA module. A photolithography process was used to make the silica solder mask pattern. The test vehicle first was sliced through the center of the solder bump and finely polished. Diffraction grating (1,200 line/mm) was replicated on the surface of solder joints. The test vehicle then was placed on the Moiré optical table by clamping on a specially designed fixture to maintain its optical position and provide electrical connections. The power supply is computer-controlled, and temperature on the test vehicle was measured digitally with an infrared thermal sensor. The results from two experiments are discussed.
In the first experiment, the Sn/Pb eutectic test module was stressed with 10 A of DC current and the calculated current density was about 175 A/cm2.
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 Figure 1. Initial Moiré fringes — upper: U-field; lower: V-field. |
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 Figure 2. Moiré fringes after two hours and 22 mins of current stressing - upper: U-field; lower: V-field. |
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The dense horizontal U-field fringes and vertical V-field fringes indicate that shear deformation was developed during stress (Figure 1). The temperature on the test vehicle was measured to increase during stress. The heat source was found to be the ends of the copper plates where they were clamped due to the high contact resistance. A finite element thermal strain analysis was performed to compare to the experiment results. Because the width of substrate copper plates was more than 10¥ wider than the thickness of the sectioned solder ball, plane strain element was used to simulate the copper plate and plane stress element was used to simulate the solder joint. A temperature change from 22° to 37°C was applied to the solder joint area and a temperature change from 22° to 57°C was applied to the both ends of the copper substrate.
The Moiré fringe is the isopleth of relative displacement on the solder surface (U-field for horizontal displacement and V-field for vertical displacement, respectively as shown in Figure 2). To compare the experiment measurement with the FE simulation result, the strain distribution along the center vertical line on the solder joint after one hour and 40 minutes of stressing was extracted with numerical differentiation (X axis is the coordinate along the center vertical line in micron and Y axis is the magnitude of strain in Figure 3).
Thermal Stressing Simulation
Figure 3 shows that both the distribution and magnitude of shear strain gxy along the vertical center line agree well in experiment and simulation. The comparison indicates that the observed displacement in this experiment was due mainly to thermal stressing caused by the joule heating. The results indicates that Moiré interferometry is a reliable technique to measure solder joint displacement under current stressing. It also suggests that to measure the displacement of solder joints caused by the current stressing alone, the temperature of the test vehicle must be controlled strictly to exclude thermal effects.
 Figure 3. Strain gxy distribution along line 3 — upper: Moiré experiment; lower: FE. |
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The well-controlled temperature during current stressing was achieved in the second Moiré interferometry experiment. Joule heating was restricted by improving the electrical contact between the test module and fixture. Lead-free solder (Sn/Ag4.0/Cu0.5) was used to fabricate the test module. In the experiment, 30 A of current was applied and by further reducing the cross section area of the solder joint, a current density of 5,000 A/cm2 was achieved. The temperature was kept almost constant at 27°C. The Moiré fringe evolution is shown in Figures 4 and 5 for U- and V-fields, respectively. After the solder joint was stressed for 170 hours, few U-field fringes developed at this high level of current density; however, some horizontal V-field fringes developed during the course of current stressing. This indicates there was little shear deformation in the solder joints. The previous experiment shows that shear deformation is dominant when thermal stressing is significant as verified by the FE simulation. Since the near constant temperature was maintained in this experiment, it is reasonable not to observe much shear deformation. The horizontal V-field fringes indicate that displacement along vertical direction (the direction of current flow) was developed gradually during the course of current stressing. Because thermal effects were excluded in this experiment, it is appropriate to believe that current stressing itself causes this vertical displacement.
More Moiré interferometry experiments will be performed for solder joints under different current densities. Based on these experimental results, a constitutive model to predict solder joint deformation under current stressing will be proposed and calibrated to be used in the numerical simulation solder joint reliability under current stressing.
Flip Chip Solder Joint Experiment
Flip chip test modules manufactured by a major corporation were tested under high-current density. The modules have a silicon test wafer mounted onto an FR-4 printed circuit board (PCB) using eutectic Sn/Pb solder. The diameter of the solder joints was about 140 µm. One A of current passed across the cross-sectioned solder joint produced a current density of more than 1.3 x 104 A/cm2. As shown in Figure 6, the microstructural evolution of solder joints was examined by SEM.
It is clear that voids were nucleated near the cathode and mass accumulation developed near the cathode during current stressing in Figure 6. Detailed results about nanoindentation, phase growth and atomic flux calculation on the flip chip solder joint are published in an earlier article.8
Conclusion
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 Figure 5. U-field fringe evolution — upper, initial; middle, 97 hours of stressing; lower, 170 hours of stressing. |
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 Figure 6. V-field fringe evolution — upper, initial; middle, 97 hours of stressing; lower, 170 hours of stressing. |
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Moiré interferometry was found to be a reliable technique to measure the in-situ deformation of solder joints under electrical current stressing. High-current density through solder joints causes solder joint deformation. Based on more Moiré experiments on BGA solder joints and microstructural tests on flip chip solder joints, a constitutive model is proposed to predict the strain-stress evolution of solder joints under current stressing. With this constitutive model, FE numerical simulations can be implemented to predict solder ball reliability under current stressing.
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 Figure 7. SEM backscatted image of solder joint (a) initial, (b) 6 hours, (c) 14.5 hours and (d) 37.5 hours. |
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REFERENCES
1. Paulasto-Krockel, M. and Hauck, T., "Flip Chip Die Attach Development for Multichip Mechatronics Power Packages," IEEE Transactions on Electronics Packaging Manufacturing, Vol. 24, No. 4, pp. 300-306, 2001.
2. Liu, X., Calata, J.N., Wang, J., and Lu, G.-Q., "The Packaging of Integrated Power Electronics Modules Using Flip-Chip Technology," CPES Seminar 1999.
3. Brandenburg, S. and Yeh, S., "Electromigration Studies of Flip Chip Bump Solder Joints," Surface Mount International Conference Proceedings, August 1998.
4. Lee, T.Y., Tu, K.N., Kuo, S.M. and Frear, D.R., "Electromigration of Eutectic Sn/Pb Solder Interconnects for Flip Chip Technology," Journal of Applied Physics, Vol. 89, No. 6, pp. 3189-3194, 2001.
5. Lee, T.Y. and Tu, K.N., "Electromigration of Eutectic Sn/Pb and Sn/Ag3.8/Cu0.7 Flip Chip Solder Bumps and Underbump Metallization," Journal of Applied Physics, Vol. 90, No. 9, pp. 4502-4508, Nov. 2001.
6. Liu, C.Y., Chen, C. and Tu, K.N., "Electromigration in Sn/Pb Solder Strips as a Function of Alloy Composition," Journal of Applied Physics, Vol. 88, No. 10, pp. 5703-5709, Nov.2000.
7. Liu, C.Y., Chen, C., Liao, C.N. and Tu, K.N., "Microstructure-Electromigration Correlation in a Thin Stripe of Eutectic Sn/Pb Solder Stressed Between Cu Electrodes," Applied Physics Letters, Vol. 75, No. 1, pp. 58-60, July1999.
8. Ye, H., Basaran, C. and Hopkins, D., "Experiment Study on Reliability of Solder Joints under Electrical Stressing — Nano-indentation, Atomic Flux Measurement," Proceedings of 2002 International Conference on Advanced Packaging and Systems, Reno, Nevada, 2002.
HUA YE, Ph.D. candidate, CEMAL BASARAN, associate professor, and DOUG HOPKINS, research associate professor, may be contacted at UB Electronic Packaging Laboratory, University at Buffalo, SUNY, Buffalo, NY 14260; E-mail: [email protected], http://www.packaging.buffalo.edu.